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[X86, AVX2] Replace inserti128 and extracti128 intrinsics with generic shuffles
This should complete the job started in r231794 and continued in r232045: We want to replace as much custom x86 shuffling via intrinsics as possible because pushing the code down the generic shuffle optimization path allows for better codegen and less complexity in LLVM. AVX2 introduced proper integer variants of the hacked integer insert/extract C intrinsics that were created for this same functionality with AVX1. This should complete the removal of insert/extract128 intrinsics. The Clang precursor patch for this change was checked in at r232109. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232120 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel
parent
740aee4b53
commit
cae9695fbb
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@ -1759,13 +1759,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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// Vector extract and insert
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx2_vextracti128 : GCCBuiltin<"__builtin_ia32_extract128i256">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v4i64_ty,
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llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx2_vinserti128 : GCCBuiltin<"__builtin_ia32_insert128i256">,
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Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty,
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llvm_v2i64_ty, llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_vextractf32x4_512 :
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GCCBuiltin<"__builtin_ia32_extractf32x4_mask">,
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Intrinsic<[llvm_v4f32_ty], [llvm_v16f32_ty, llvm_i8_ty,
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@ -4966,28 +4966,6 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
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setValue(&I, Res);
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return nullptr;
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}
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case Intrinsic::x86_avx2_vinserti128: {
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EVT DestVT = TLI.getValueType(I.getType());
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EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
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uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
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ElVT.getVectorNumElements();
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Res =
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DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
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getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)),
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DAG.getConstant(Idx, TLI.getVectorIdxTy()));
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setValue(&I, Res);
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return nullptr;
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}
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case Intrinsic::x86_avx2_vextracti128: {
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EVT DestVT = TLI.getValueType(I.getType());
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uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
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DestVT.getVectorNumElements();
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Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
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getValue(I.getArgOperand(0)),
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DAG.getConstant(Idx, TLI.getVectorIdxTy()));
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setValue(&I, Res);
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return nullptr;
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}
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case Intrinsic::convertff:
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case Intrinsic::convertfsi:
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case Intrinsic::convertfui:
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@ -161,9 +161,11 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) {
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Name == "x86.avx.vinsertf128.pd.256" ||
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Name == "x86.avx.vinsertf128.ps.256" ||
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Name == "x86.avx.vinsertf128.si.256" ||
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Name == "x86.avx2.vinserti128" ||
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Name == "x86.avx.vextractf128.pd.256" ||
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Name == "x86.avx.vextractf128.ps.256" ||
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Name == "x86.avx.vextractf128.si.256" ||
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Name == "x86.avx2.vextracti128" ||
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Name == "x86.avx.movnt.dq.256" ||
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Name == "x86.avx.movnt.pd.256" ||
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Name == "x86.avx.movnt.ps.256" ||
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@ -634,7 +636,8 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
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Rep = Builder.CreateShuffleVector(Op0, Op1, ConstantVector::get(Idxs));
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} else if (Name == "llvm.x86.avx.vinsertf128.pd.256" ||
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Name == "llvm.x86.avx.vinsertf128.ps.256" ||
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Name == "llvm.x86.avx.vinsertf128.si.256") {
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Name == "llvm.x86.avx.vinsertf128.si.256" ||
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Name == "llvm.x86.avx2.vinserti128") {
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Value *Op0 = CI->getArgOperand(0);
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Value *Op1 = CI->getArgOperand(1);
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unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue();
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@ -679,7 +682,8 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
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Rep = Builder.CreateShuffleVector(Op0, Rep, ConstantVector::get(Idxs2));
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} else if (Name == "llvm.x86.avx.vextractf128.pd.256" ||
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Name == "llvm.x86.avx.vextractf128.ps.256" ||
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Name == "llvm.x86.avx.vextractf128.si.256") {
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Name == "llvm.x86.avx.vextractf128.si.256" ||
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Name == "llvm.x86.avx2.vextracti128") {
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Value *Op0 = CI->getArgOperand(0);
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unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
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VectorType *VecTy = cast<VectorType>(CI->getType());
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@ -8595,9 +8595,7 @@ def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
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//
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def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
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(ins VR256:$src1, u8imm:$src2),
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"vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst,
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(int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
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"vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
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Sched<[WriteShuffle256]>, VEX, VEX_L;
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let hasSideEffects = 0, mayStore = 1 in
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def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
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@ -1,4 +1,4 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mcpu=core-avx2 -mattr=avx2 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mattr=avx2 | FileCheck %s
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define <16 x i16> @test_x86_avx2_pblendw(<16 x i16> %a0, <16 x i16> %a1) {
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; CHECK: vpblendw
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@ -62,3 +62,24 @@ define <4 x i64> @test_x86_avx2_psrl_dq(<4 x i64> %a0) {
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ret <4 x i64> %res
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}
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declare <4 x i64> @llvm.x86.avx2.psrl.dq(<4 x i64>, i32) nounwind readnone
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define <2 x i64> @test_x86_avx2_vextracti128(<4 x i64> %a0) {
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; CHECK-LABEL: test_x86_avx2_vextracti128:
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; CHECK: vextracti128
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%res = call <2 x i64> @llvm.x86.avx2.vextracti128(<4 x i64> %a0, i8 7)
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ret <2 x i64> %res
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}
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declare <2 x i64> @llvm.x86.avx2.vextracti128(<4 x i64>, i8) nounwind readnone
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define <4 x i64> @test_x86_avx2_vinserti128(<4 x i64> %a0, <2 x i64> %a1) {
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; CHECK-LABEL: test_x86_avx2_vinserti128:
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; CHECK: vinserti128
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%res = call <4 x i64> @llvm.x86.avx2.vinserti128(<4 x i64> %a0, <2 x i64> %a1, i8 7)
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ret <4 x i64> %res
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}
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declare <4 x i64> @llvm.x86.avx2.vinserti128(<4 x i64>, <2 x i64>, i8) nounwind readnone
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@ -1,4 +1,4 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mcpu=core-avx2 -mattr=avx2 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mattr=avx2 | FileCheck %s
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define <16 x i16> @test_x86_avx2_packssdw(<8 x i32> %a0, <8 x i32> %a1) {
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; CHECK: vpackssdw
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@ -775,22 +775,6 @@ define <4 x i64> @test_x86_avx2_vperm2i128(<4 x i64> %a0, <4 x i64> %a1) {
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declare <4 x i64> @llvm.x86.avx2.vperm2i128(<4 x i64>, <4 x i64>, i8) nounwind readonly
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define <2 x i64> @test_x86_avx2_vextracti128(<4 x i64> %a0) {
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; CHECK: vextracti128
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%res = call <2 x i64> @llvm.x86.avx2.vextracti128(<4 x i64> %a0, i8 7) ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %res
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}
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declare <2 x i64> @llvm.x86.avx2.vextracti128(<4 x i64>, i8) nounwind readnone
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define <4 x i64> @test_x86_avx2_vinserti128(<4 x i64> %a0, <2 x i64> %a1) {
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; CHECK: vinserti128
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%res = call <4 x i64> @llvm.x86.avx2.vinserti128(<4 x i64> %a0, <2 x i64> %a1, i8 7) ; <<4 x i64>> [#uses=1]
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ret <4 x i64> %res
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}
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declare <4 x i64> @llvm.x86.avx2.vinserti128(<4 x i64>, <2 x i64>, i8) nounwind readnone
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define <2 x i64> @test_x86_avx2_maskload_q(i8* %a0, <2 x i64> %a1) {
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; CHECK: vpmaskmovq
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%res = call <2 x i64> @llvm.x86.avx2.maskload.q(i8* %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
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