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fold and (shl X, C1), C2 -> rlwinm when possible. Many other cases are possible,
include and (srl) and the inverses (shl and) etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21820 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1845,27 +1845,46 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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return Result;
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}
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}
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Tmp1 = SelectExpr(N.getOperand(0));
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// FIXME: should add check in getImmediateForOpcode to return a value
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// indicating the immediate is a run of set bits so we can emit a bitfield
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// clear with RLWINM instead.
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switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
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default: assert(0 && "unhandled result code");
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case 0: // No immediate
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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Opc = Recording ? PPC::ANDo : PPC::AND;
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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break;
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case 1: // Low immediate
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, PPC::ANDIo, 2, Result).addReg(Tmp1).addImm(Tmp2);
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break;
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case 2: // Shifted immediate
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, PPC::ANDISo, 2, Result).addReg(Tmp1).addImm(Tmp2);
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break;
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case 5: // Bitfield mask
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Opc = Recording ? PPC::RLWINMo : PPC::RLWINM;
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Tmp3 = Tmp2 >> 16; // MB
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Tmp2 &= 0xFFFF; // ME
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if (N.getOperand(0).getOpcode() == ISD::SRL)
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if (ConstantSDNode *SA =
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dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
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// We can fold the RLWINM and the SRL together if the mask is
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// clearing the top bits which are rotated around.
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unsigned RotAmt = 32-(SA->getValue() & 31);
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if (Tmp2 <= RotAmt) {
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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BuildMI(BB, Opc, 4, Result).addReg(Tmp1).addImm(RotAmt)
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.addImm(Tmp3).addImm(Tmp2);
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break;
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}
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}
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Opc, 4, Result).addReg(Tmp1).addImm(0)
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.addImm(Tmp3).addImm(Tmp2);
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break;
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