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Follow up to Jim's r138278. This fixes commuteInstruction so it handles two-address instructions correctly. I'll let Jim add a test case. :-)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138289 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-08-22 23:04:56 +00:00
parent 10fd9ad8f3
commit cb08f18d5b
1 changed files with 12 additions and 10 deletions
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22
lib/CodeGen/TargetInstrInfoImpl.cpp
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@ -74,23 +74,25 @@ MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
"This only knows how to commute register operands so far"); "This only knows how to commute register operands so far");
unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
unsigned Reg1 = MI->getOperand(Idx1).getReg(); unsigned Reg1 = MI->getOperand(Idx1).getReg();
unsigned Reg2 = MI->getOperand(Idx2).getReg(); unsigned Reg2 = MI->getOperand(Idx2).getReg();
bool Reg1IsKill = MI->getOperand(Idx1).isKill(); bool Reg1IsKill = MI->getOperand(Idx1).isKill();
bool Reg2IsKill = MI->getOperand(Idx2).isKill(); bool Reg2IsKill = MI->getOperand(Idx2).isKill();
bool ChangeReg0 = false; // If destination is tied to either of the commuted source register, then
if (HasDef && MI->getOperand(0).getReg() == Reg1) { // it must be updated.
// Must be two address instruction! if (HasDef && Reg0 == Reg1 &&
assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) && MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
"Expecting a two-address instruction!");
Reg2IsKill = false; Reg2IsKill = false;
ChangeReg0 = true; Reg0 = Reg2;
} else if (HasDef && Reg0 == Reg2 &&
MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
Reg1IsKill = false;
Reg0 = Reg1;
} }
if (NewMI) { if (NewMI) {
// Create a new instruction. // Create a new instruction.
unsigned Reg0 = HasDef
? (ChangeReg0 ? Reg2 : MI->getOperand(0).getReg()) : 0;
bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false; bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false;
MachineFunction &MF = *MI->getParent()->getParent(); MachineFunction &MF = *MI->getParent()->getParent();
if (HasDef) if (HasDef)
@ -104,8 +106,8 @@ MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
.addReg(Reg1, getKillRegState(Reg2IsKill)); .addReg(Reg1, getKillRegState(Reg2IsKill));
} }
if (ChangeReg0) if (HasDef)
MI->getOperand(0).setReg(Reg2); MI->getOperand(0).setReg(Reg0);
MI->getOperand(Idx2).setReg(Reg1); MI->getOperand(Idx2).setReg(Reg1);
MI->getOperand(Idx1).setReg(Reg2); MI->getOperand(Idx1).setReg(Reg2);
MI->getOperand(Idx2).setIsKill(Reg1IsKill); MI->getOperand(Idx2).setIsKill(Reg1IsKill);