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Disable folding loads into tail call in 32-bit PIC mode. It can introduce illegal code like this:
addl $12, %esp popl %esi popl %edi popl %ebx popl %ebp jmpl *__Block_deallocator-L1$pb(%esi) # TAILCALL The problem is the global base register is assigned GR32 register class. TCRETURNmi needs the registers making up the address mode to have the GR32_TC register class. The *proper* fix is for X86DAGToDAGISel::getGlobalBaseReg() to return a copy from the global base register of the machine function rather than returning the register itself. But that has the potential of causing it to be coalesced to a more restrictive register class: GR32_TC. It can introduce additional copies and spills. For something as important the PIC base, it's not worth it especially since this is not an issue on 64-bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99455 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -325,6 +325,7 @@ def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
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def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
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"TM.getCodeModel() == CodeModel::Kernel">;
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def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
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def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
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def OptForSize : Predicate<"OptForSize">;
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def OptForSpeed : Predicate<"!OptForSize">;
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def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
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@ -4346,9 +4347,12 @@ def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
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(TCRETURNri GR32_TC:$dst, imm:$off)>,
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Requires<[In32BitMode]>;
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// FIXME: This is disabled for 32-bit PIC mode because the global base
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// register which is part of the address mode may be assigned a
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// callee-saved register.
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def : Pat<(X86tcret (load addr:$dst), imm:$off),
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(TCRETURNmi addr:$dst, imm:$off)>,
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Requires<[In32BitMode]>;
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Requires<[In32BitMode, IsNotPIC]>;
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def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
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(TCRETURNdi texternalsym:$dst, imm:$off)>,
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