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* Promote all 1 bit entities to 8 bit.
* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit zextload. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24726 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
d0f6d18aa8
commit
cb17bac3a3
@ -150,7 +150,7 @@ def SDTStore : SDTypeProfile<0, 2, [ // store
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SDTCisPtrTy<1>
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]>;
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def SDTIntExtLoad : SDTypeProfile<1, 3, [ // sextload, zextload
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def SDTIntExtLoad : SDTypeProfile<1, 3, [ // sextload, zextload, extload
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SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
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]>;
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@ -261,6 +261,7 @@ def store : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>;
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// below) which pass in a dummy srcvalue node which tblgen will skip over.
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def sextld : SDNode<"ISD::SEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>;
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def zextld : SDNode<"ISD::ZEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>;
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def extld : SDNode<"ISD::EXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>;
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//===----------------------------------------------------------------------===//
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// Selection DAG Condition Codes
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@ -333,6 +334,8 @@ def sextload : PatFrag<(ops node:$ptr, node:$vt),
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(sextld node:$ptr, srcvalue:$dummy, node:$vt)>;
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def zextload : PatFrag<(ops node:$ptr, node:$vt),
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(zextld node:$ptr, srcvalue:$dummy, node:$vt)>;
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def extload : PatFrag<(ops node:$ptr, node:$vt),
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(extld node:$ptr, srcvalue:$dummy, node:$vt)>;
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// setcc convenience fragments.
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def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
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@ -22,7 +22,6 @@
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/Statistic.h"
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#include <set>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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@ -96,8 +95,6 @@ namespace {
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private:
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SDOperand Select(SDOperand N);
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bool isFoldableLoad(SDOperand Op, SDOperand OtherOp,
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bool FloatPromoteOk = false);
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bool MatchAddress(SDOperand N, X86ISelAddressMode &AM);
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bool SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp);
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@ -362,68 +359,6 @@ bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand &Base, SDOperand &Sca
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return false;
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}
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/// NodeTransitivelyUsesValue - Return true if N or any of its uses uses Op.
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/// The DAG cannot have cycles in it, by definition, so the visited set is not
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/// needed to prevent infinite loops. The DAG CAN, however, have unbounded
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/// reuse, so it prevents exponential cases.
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///
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static bool NodeTransitivelyUsesValue(SDOperand N, SDOperand Op,
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std::set<SDNode*> &Visited) {
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if (N == Op) return true; // Found it.
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SDNode *Node = N.Val;
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if (Node->getNumOperands() == 0 || // Leaf?
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Node->getNodeDepth() <= Op.getNodeDepth()) return false; // Can't find it?
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if (!Visited.insert(Node).second) return false; // Already visited?
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// Recurse for the first N-1 operands.
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for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
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if (NodeTransitivelyUsesValue(Node->getOperand(i), Op, Visited))
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return true;
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// Tail recurse for the last operand.
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return NodeTransitivelyUsesValue(Node->getOperand(0), Op, Visited);
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}
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/// isFoldableLoad - Return true if this is a load instruction that can safely
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/// be folded into an operation that uses it.
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bool X86DAGToDAGISel::isFoldableLoad(SDOperand Op, SDOperand OtherOp,
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bool FloatPromoteOk) {
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if (Op.getOpcode() == ISD::LOAD) {
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// FIXME: currently can't fold constant pool indexes.
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if (isa<ConstantPoolSDNode>(Op.getOperand(1)))
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return false;
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} else if (FloatPromoteOk && Op.getOpcode() == ISD::EXTLOAD &&
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cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::f32) {
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// FIXME: currently can't fold constant pool indexes.
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if (isa<ConstantPoolSDNode>(Op.getOperand(1)))
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return false;
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} else {
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return false;
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}
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// If this load has already been emitted, we clearly can't fold it.
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assert(Op.ResNo == 0 && "Not a use of the value of the load?");
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if (CodeGenMap.count(Op.getValue(1))) return false;
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assert(!CodeGenMap.count(Op.getValue(0)) &&
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"Value in map but not token chain?");
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assert(!CodeGenMap.count(Op.getValue(1)) &&
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"Token lowered but value not in map?");
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// If there is not just one use of its value, we cannot fold.
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if (!Op.Val->hasNUsesOfValue(1, 0)) return false;
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// Finally, we cannot fold the load into the operation if this would induce a
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// cycle into the resultant dag. To check for this, see if OtherOp (the other
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// operand of the operation we are folding the load into) can possible use the
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// chain node defined by the load.
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if (OtherOp.Val && !Op.Val->hasNUsesOfValue(0, 1)) { // Has uses of chain?
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std::set<SDNode*> Visited;
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if (NodeTransitivelyUsesValue(OtherOp, Op.getValue(1), Visited))
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return false;
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}
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return true;
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}
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SDOperand X86DAGToDAGISel::Select(SDOperand N) {
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SDNode *Node = N.Val;
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MVT::ValueType NVT = Node->getValueType(0);
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@ -455,48 +390,6 @@ SDOperand X86DAGToDAGISel::Select(SDOperand N) {
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}
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break;
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case ISD::ANY_EXTEND: // treat any extend like zext
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case ISD::ZERO_EXTEND: {
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SDOperand N0 = N.getOperand(0);
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if (N0.getValueType() == MVT::i1) {
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// FIXME: This hack is here for zero extension casts from bool to i8.
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// This would not be needed if bools were promoted by Legalize.
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if (NVT == MVT::i8) {
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Opc = X86::MOV8rr;
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} else if (!isFoldableLoad(N0, SDOperand())) {
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switch (NVT) {
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default: assert(0 && "Cannot zero extend to this type!");
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case MVT::i16: Opc = X86::MOVZX16rr8; break;
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case MVT::i32: Opc = X86::MOVZX32rr8; break;
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}
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} else {
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switch (NVT) {
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default: assert(0 && "Cannot zero extend to this type!");
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case MVT::i16: Opc = X86::MOVZX16rm8; break;
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case MVT::i32: Opc = X86::MOVZX32rm8; break;
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}
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SDOperand Chain = Select(N0.getOperand(0));
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SDOperand Base, Scale, Index, Disp;
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(void) SelectAddr(N0.getOperand(1), Base, Scale, Index, Disp);
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SDOperand Result = CurDAG->getTargetNode(Opc, NVT,
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MVT::Other, Base, Scale,
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Index, Disp, Chain);
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CodeGenMap[N.getValue(0)] = Result;
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Chain = CodeGenMap[N.getValue(1)] = Result.getValue(1);
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return (N.ResNo) ? Chain : Result.getValue(0);
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}
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SDOperand Tmp0 = Select(Node->getOperand(0));
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if (Node->hasOneUse())
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return CurDAG->SelectNodeTo(Node, Opc, NVT, Tmp0);
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else
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return CodeGenMap[N] = CurDAG->getTargetNode(Opc, NVT, Tmp0);
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}
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// Other cases are autogenerated.
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break;
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}
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case ISD::RET: {
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SDOperand Chain = Node->getOperand(0); // Token chain.
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unsigned NumOps = Node->getNumOperands();
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@ -41,9 +41,6 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
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// Set up the register classes.
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// FIXME: Eliminate these two classes when legalize can handle promotions
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// well.
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addRegisterClass(MVT::i1, X86::R8RegisterClass);
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addRegisterClass(MVT::i8, X86::R8RegisterClass);
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addRegisterClass(MVT::i16, X86::R16RegisterClass);
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addRegisterClass(MVT::i32, X86::R32RegisterClass);
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@ -180,6 +180,8 @@ def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i8))>;
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def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i8))>;
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def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i16))>;
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def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extload node:$ptr, i1))>;
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//===----------------------------------------------------------------------===//
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// Instruction templates...
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@ -432,9 +434,6 @@ def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src),
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"mov{l} {$src, $dst|$dst, $src}",
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[(store R32:$src, addr:$dst)]>;
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// Handling 1 bit load
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def : Pat<(i1 (load addr:$src)), (MOV8rm addr:$src)>;
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//===----------------------------------------------------------------------===//
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// Fixed-Register Multiplication and Division Instructions...
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//
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@ -1720,6 +1719,9 @@ def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>;
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def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
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def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
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// Handling 1 bit extload
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def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
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//===----------------------------------------------------------------------===//
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// XMM Floating point support (requires SSE2)
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//===----------------------------------------------------------------------===//
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