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More h-registers tricks: folding zext nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72558 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1607,6 +1607,13 @@ def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
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(EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
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x86_subreg_8bit_hi))>,
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Requires<[In64BitMode]>;
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def : Pat<(i64 (zext (srl_su GR32:$src, (i8 8)))),
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(SUBREG_TO_REG
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(i64 0),
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(MOVZX32_NOREXrr8
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(EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
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x86_subreg_8bit_hi)),
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x86_subreg_32bit)>;
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def : Pat<(srl_su GR16:$src, (i8 8)),
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(EXTRACT_SUBREG
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(MOVZX32_NOREXrr8
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@ -1614,6 +1621,18 @@ def : Pat<(srl_su GR16:$src, (i8 8)),
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x86_subreg_8bit_hi)),
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x86_subreg_16bit)>,
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Requires<[In64BitMode]>;
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def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
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(MOVZX32_NOREXrr8
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(EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
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x86_subreg_8bit_hi))>,
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Requires<[In64BitMode]>;
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def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
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(SUBREG_TO_REG
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(i64 0),
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(MOVZX32_NOREXrr8
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(EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
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x86_subreg_8bit_hi)),
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x86_subreg_32bit)>;
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// h-register extract and store.
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def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
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@ -3538,6 +3538,10 @@ def : Pat<(srl_su GR16:$src, (i8 8)),
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x86_subreg_8bit_hi)),
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x86_subreg_16bit)>,
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Requires<[In32BitMode]>;
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def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
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(MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
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x86_subreg_8bit_hi))>,
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Requires<[In32BitMode]>;
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def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
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(MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
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x86_subreg_8bit_hi))>,
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12
test/CodeGen/X86/h-registers-3.ll
Normal file
12
test/CodeGen/X86/h-registers-3.ll
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@ -0,0 +1,12 @@
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; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 1
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; RUN: llvm-as < %s | llc -march=x86-64 | grep mov | count 1
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define zeroext i8 @foo() nounwind ssp {
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entry:
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%0 = tail call zeroext i16 (...)* @bar() nounwind
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%1 = lshr i16 %0, 8
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%2 = trunc i16 %1 to i8
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ret i8 %2
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}
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declare zeroext i16 @bar(...)
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40
test/CodeGen/X86/remat-mov0.ll
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40
test/CodeGen/X86/remat-mov0.ll
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@ -0,0 +1,40 @@
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; RUN: llvm-as < %s | llc -march=x86 | grep xor | count 2
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%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
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%struct.ImgT = type { i8, i8*, i8*, %struct.FILE*, i32, i32, i32, i32, i8*, double*, float*, float*, float*, i32*, double, double, i32*, double*, i32*, i32* }
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%struct._CompT = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, i8, %struct._PixT*, %struct._CompT*, i8, %struct._CompT* }
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%struct._PixT = type { i32, i32, %struct._PixT* }
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%struct.__sFILEX = type opaque
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%struct.__sbuf = type { i8*, i32 }
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declare fastcc void @MergeComponents(%struct._CompT*, %struct._CompT*, %struct._CompT*, %struct._CompT**, %struct.ImgT*) nounwind
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define fastcc void @MergeToLeft(%struct._CompT* %comp, %struct._CompT** %head, %struct.ImgT* %img) nounwind {
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entry:
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br label %bb208
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bb105: ; preds = %bb200
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br i1 false, label %bb197, label %bb149
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bb149: ; preds = %bb105
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%tmp151 = getelementptr %struct._CompT* %comp, i32 0, i32 0 ; <i32*> [#uses=1]
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br label %bb193
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bb193: ; preds = %bb184, %bb149
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%tmp196 = load i32* %tmp151, align 4 ; <i32> [#uses=1]
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br label %bb197
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bb197: ; preds = %bb193, %bb105
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%last_comp.0 = phi i32 [ %tmp196, %bb193 ], [ 0, %bb105 ] ; <i32> [#uses=0]
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%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
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br label %bb200
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bb200: ; preds = %bb208, %bb197
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%indvar = phi i32 [ 0, %bb208 ], [ %indvar.next, %bb197 ] ; <i32> [#uses=2]
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%xm.0 = sub i32 %indvar, 0 ; <i32> [#uses=1]
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%tmp202 = icmp slt i32 %xm.0, 1 ; <i1> [#uses=1]
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br i1 %tmp202, label %bb105, label %bb208
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bb208: ; preds = %bb200, %entry
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br label %bb200
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}
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