mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-02 17:55:18 +00:00
MIPS DSP: ABSQ_S.PH instruction sub-class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164787 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
23bb38f034
commit
cb39aa05af
@ -99,6 +99,33 @@ class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst {
|
||||
let Inst{5-0} = 0b010001;
|
||||
}
|
||||
|
||||
// ABSQ_S.PH sub-class format.
|
||||
class ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst {
|
||||
bits<5> rd;
|
||||
bits<5> rt;
|
||||
|
||||
let Opcode = SPECIAL3_OPCODE.V;
|
||||
|
||||
let Inst{25-21} = 0;
|
||||
let Inst{20-16} = rt;
|
||||
let Inst{15-11} = rd;
|
||||
let Inst{10-6} = op;
|
||||
let Inst{5-0} = 0b010010;
|
||||
}
|
||||
|
||||
|
||||
class REPL_FMT<bits<5> op> : DSPInst {
|
||||
bits<5> rd;
|
||||
bits<10> imm;
|
||||
|
||||
let Opcode = SPECIAL3_OPCODE.V;
|
||||
|
||||
let Inst{25-16} = imm;
|
||||
let Inst{15-11} = rd;
|
||||
let Inst{10-6} = op;
|
||||
let Inst{5-0} = 0b010010;
|
||||
}
|
||||
|
||||
// SHLL.QB sub-class format.
|
||||
class SHLL_QB_FMT<bits<5> op> : DSPInst {
|
||||
bits<5> rd;
|
||||
|
||||
@ -106,10 +106,22 @@ class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
|
||||
class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
|
||||
class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
|
||||
class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
|
||||
class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
|
||||
class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
|
||||
class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
|
||||
class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
|
||||
class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
|
||||
class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
|
||||
class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
|
||||
class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
|
||||
class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
|
||||
class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
|
||||
class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
|
||||
class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
|
||||
class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
|
||||
class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
|
||||
class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
|
||||
class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
|
||||
class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
|
||||
class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
|
||||
class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
|
||||
@ -159,7 +171,12 @@ class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
|
||||
class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
|
||||
class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
|
||||
class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
|
||||
class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
|
||||
class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
|
||||
class REPL_QB_ENC : REPL_FMT<0b00010>;
|
||||
class REPL_PH_ENC : REPL_FMT<0b01010>;
|
||||
class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
|
||||
class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
|
||||
class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
|
||||
class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
|
||||
class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
|
||||
@ -188,6 +205,7 @@ class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
|
||||
class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
|
||||
class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
|
||||
class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
|
||||
class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
|
||||
class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
|
||||
class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
|
||||
class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
|
||||
@ -265,6 +283,27 @@ class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
string Constraints = "$src = $rt";
|
||||
}
|
||||
|
||||
class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
InstrItinClass itin, RegisterClass RCD,
|
||||
RegisterClass RCT = RCD> {
|
||||
dag OutOperandList = (outs RCD:$rd);
|
||||
dag InOperandList = (ins RCT:$rt);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
|
||||
list<dag> Pattern = [(set RCD:$rd, (OpNode RCT:$rt))];
|
||||
InstrItinClass Itinerary = itin;
|
||||
list<Register> Defs = [DSPCtrl];
|
||||
}
|
||||
|
||||
class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
ImmLeaf immPat, InstrItinClass itin, RegisterClass RC> {
|
||||
dag OutOperandList = (outs RC:$rd);
|
||||
dag InOperandList = (ins uimm16:$imm);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
|
||||
list<dag> Pattern = [(set RC:$rd, (OpNode immPat:$imm))];
|
||||
InstrItinClass Itinerary = itin;
|
||||
list<Register> Defs = [DSPCtrl];
|
||||
}
|
||||
|
||||
class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
InstrItinClass itin, RegisterClass RC> {
|
||||
dag OutOperandList = (outs RC:$rd);
|
||||
@ -450,6 +489,13 @@ class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
|
||||
NoItinerary, CPURegs, DSPRegs>,
|
||||
ClearDefs;
|
||||
|
||||
// Absolute value
|
||||
class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
|
||||
NoItinerary, DSPRegs>;
|
||||
|
||||
class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
|
||||
NoItinerary, CPURegs>;
|
||||
|
||||
// Precision reduce/expand
|
||||
class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
|
||||
int_mips_precrq_qb_ph,
|
||||
@ -471,6 +517,56 @@ class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
|
||||
NoItinerary, DSPRegs,
|
||||
DSPRegs>;
|
||||
|
||||
class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
|
||||
int_mips_preceq_w_phl,
|
||||
NoItinerary, CPURegs, DSPRegs>,
|
||||
ClearDefs;
|
||||
|
||||
class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
|
||||
int_mips_preceq_w_phr,
|
||||
NoItinerary, CPURegs, DSPRegs>,
|
||||
ClearDefs;
|
||||
|
||||
class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
|
||||
int_mips_precequ_ph_qbl,
|
||||
NoItinerary, DSPRegs>,
|
||||
ClearDefs;
|
||||
|
||||
class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
|
||||
int_mips_precequ_ph_qbr,
|
||||
NoItinerary, DSPRegs>,
|
||||
ClearDefs;
|
||||
|
||||
class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
|
||||
int_mips_precequ_ph_qbla,
|
||||
NoItinerary, DSPRegs>,
|
||||
ClearDefs;
|
||||
|
||||
class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
|
||||
int_mips_precequ_ph_qbra,
|
||||
NoItinerary, DSPRegs>,
|
||||
ClearDefs;
|
||||
|
||||
class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
|
||||
int_mips_preceu_ph_qbl,
|
||||
NoItinerary, DSPRegs>,
|
||||
ClearDefs;
|
||||
|
||||
class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
|
||||
int_mips_preceu_ph_qbr,
|
||||
NoItinerary, DSPRegs>,
|
||||
ClearDefs;
|
||||
|
||||
class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
|
||||
int_mips_preceu_ph_qbla,
|
||||
NoItinerary, DSPRegs>,
|
||||
ClearDefs;
|
||||
|
||||
class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
|
||||
int_mips_preceu_ph_qbra,
|
||||
NoItinerary, DSPRegs>,
|
||||
ClearDefs;
|
||||
|
||||
// Shift
|
||||
class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", int_mips_shll_qb, immZExt3,
|
||||
NoItinerary, DSPRegs>;
|
||||
@ -625,10 +721,27 @@ class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
|
||||
IsCommutable;
|
||||
|
||||
// Misc
|
||||
class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
|
||||
NoItinerary, CPURegs>, ClearDefs;
|
||||
|
||||
class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
|
||||
NoItinerary, DSPRegs, DSPRegs>,
|
||||
ClearDefs;
|
||||
|
||||
class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8,
|
||||
NoItinerary, DSPRegs>, ClearDefs;
|
||||
|
||||
class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10,
|
||||
NoItinerary, DSPRegs>, ClearDefs;
|
||||
|
||||
class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
|
||||
NoItinerary, DSPRegs, CPURegs>,
|
||||
ClearDefs;
|
||||
|
||||
class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
|
||||
NoItinerary, DSPRegs, CPURegs>,
|
||||
ClearDefs;
|
||||
|
||||
class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
|
||||
NoItinerary, DSPRegs, DSPRegs>,
|
||||
ClearDefs, UseDSPCtrl;
|
||||
@ -712,6 +825,10 @@ class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
|
||||
NoItinerary, CPURegs, DSPRegs>,
|
||||
IsCommutable;
|
||||
|
||||
// Absolute
|
||||
class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
|
||||
NoItinerary, DSPRegs>;
|
||||
|
||||
// Multiplication
|
||||
class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
|
||||
NoItinerary, DSPRegs, DSPRegs>,
|
||||
@ -790,10 +907,22 @@ def ADDSC : ADDSC_ENC, ADDSC_DESC;
|
||||
def ADDWC : ADDWC_ENC, ADDWC_DESC;
|
||||
def MODSUB : MODSUB_ENC, MODSUB_DESC;
|
||||
def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
|
||||
def ABSQ_S_PH : ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
|
||||
def ABSQ_S_W : ABSQ_S_W_ENC, ABSQ_S_W_DESC;
|
||||
def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
|
||||
def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
|
||||
def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
|
||||
def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
|
||||
def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
|
||||
def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
|
||||
def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
|
||||
def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
|
||||
def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
|
||||
def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
|
||||
def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
|
||||
def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
|
||||
def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
|
||||
def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
|
||||
def SHLL_QB : SHLL_QB_ENC, SHLL_QB_DESC;
|
||||
def SHLLV_QB : SHLLV_QB_ENC, SHLLV_QB_DESC;
|
||||
def SHRL_QB : SHRL_QB_ENC, SHRL_QB_DESC;
|
||||
@ -843,7 +972,12 @@ def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
|
||||
def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
|
||||
def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
|
||||
def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
|
||||
def BITREV : BITREV_ENC, BITREV_DESC;
|
||||
def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
|
||||
def REPL_QB : REPL_QB_ENC, REPL_QB_DESC;
|
||||
def REPL_PH : REPL_PH_ENC, REPL_PH_DESC;
|
||||
def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC;
|
||||
def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC;
|
||||
def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
|
||||
def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
|
||||
def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
|
||||
@ -874,6 +1008,7 @@ def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
|
||||
def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
|
||||
def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
|
||||
def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
|
||||
def ABSQ_S_QB : ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
|
||||
def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
|
||||
def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC;
|
||||
def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
|
||||
|
||||
@ -996,3 +996,205 @@ entry:
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define { i32 } @test__builtin_mips_absq_s_ph1(i32 %i0, i32 %a0.coerce) nounwind {
|
||||
entry:
|
||||
; CHECK: absq_s.ph
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = tail call <2 x i16> @llvm.mips.absq.s.ph(<2 x i16> %0)
|
||||
%2 = bitcast <2 x i16> %1 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.absq.s.ph(<2 x i16>) nounwind
|
||||
|
||||
define i32 @test__builtin_mips_absq_s_w1(i32 %i0, i32 %a0) nounwind {
|
||||
entry:
|
||||
; CHECK: absq_s.w
|
||||
|
||||
%0 = tail call i32 @llvm.mips.absq.s.w(i32 %a0)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.mips.absq.s.w(i32) nounwind
|
||||
|
||||
define i32 @test__builtin_mips_preceq_w_phl1(i32 %i0, i32 %a0.coerce) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: preceq.w.phl
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = tail call i32 @llvm.mips.preceq.w.phl(<2 x i16> %0)
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
declare i32 @llvm.mips.preceq.w.phl(<2 x i16>) nounwind readnone
|
||||
|
||||
define i32 @test__builtin_mips_preceq_w_phr1(i32 %i0, i32 %a0.coerce) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: preceq.w.phr
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <2 x i16>
|
||||
%1 = tail call i32 @llvm.mips.preceq.w.phr(<2 x i16> %0)
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
declare i32 @llvm.mips.preceq.w.phr(<2 x i16>) nounwind readnone
|
||||
|
||||
define { i32 } @test__builtin_mips_precequ_ph_qbl1(i32 %i0, i32 %a0.coerce) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: precequ.ph.qbl
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbl(<4 x i8> %0)
|
||||
%2 = bitcast <2 x i16> %1 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.precequ.ph.qbl(<4 x i8>) nounwind readnone
|
||||
|
||||
define { i32 } @test__builtin_mips_precequ_ph_qbr1(i32 %i0, i32 %a0.coerce) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: precequ.ph.qbr
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbr(<4 x i8> %0)
|
||||
%2 = bitcast <2 x i16> %1 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.precequ.ph.qbr(<4 x i8>) nounwind readnone
|
||||
|
||||
define { i32 } @test__builtin_mips_precequ_ph_qbla1(i32 %i0, i32 %a0.coerce) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: precequ.ph.qbla
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbla(<4 x i8> %0)
|
||||
%2 = bitcast <2 x i16> %1 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.precequ.ph.qbla(<4 x i8>) nounwind readnone
|
||||
|
||||
define { i32 } @test__builtin_mips_precequ_ph_qbra1(i32 %i0, i32 %a0.coerce) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: precequ.ph.qbra
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbra(<4 x i8> %0)
|
||||
%2 = bitcast <2 x i16> %1 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.precequ.ph.qbra(<4 x i8>) nounwind readnone
|
||||
|
||||
define { i32 } @test__builtin_mips_preceu_ph_qbl1(i32 %i0, i32 %a0.coerce) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: preceu.ph.qbl
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbl(<4 x i8> %0)
|
||||
%2 = bitcast <2 x i16> %1 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.preceu.ph.qbl(<4 x i8>) nounwind readnone
|
||||
|
||||
define { i32 } @test__builtin_mips_preceu_ph_qbr1(i32 %i0, i32 %a0.coerce) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: preceu.ph.qbr
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbr(<4 x i8> %0)
|
||||
%2 = bitcast <2 x i16> %1 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.preceu.ph.qbr(<4 x i8>) nounwind readnone
|
||||
|
||||
define { i32 } @test__builtin_mips_preceu_ph_qbla1(i32 %i0, i32 %a0.coerce) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: preceu.ph.qbla
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbla(<4 x i8> %0)
|
||||
%2 = bitcast <2 x i16> %1 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.preceu.ph.qbla(<4 x i8>) nounwind readnone
|
||||
|
||||
define { i32 } @test__builtin_mips_preceu_ph_qbra1(i32 %i0, i32 %a0.coerce) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: preceu.ph.qbra
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbra(<4 x i8> %0)
|
||||
%2 = bitcast <2 x i16> %1 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.preceu.ph.qbra(<4 x i8>) nounwind readnone
|
||||
|
||||
define { i32 } @test__builtin_mips_repl_qb1(i32 %i0) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: repl.qb
|
||||
|
||||
%0 = tail call <4 x i8> @llvm.mips.repl.qb(i32 127)
|
||||
%1 = bitcast <4 x i8> %0 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <4 x i8> @llvm.mips.repl.qb(i32) nounwind readnone
|
||||
|
||||
define { i32 } @test__builtin_mips_repl_qb2(i32 %i0, i32 %a0) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: replv.qb
|
||||
|
||||
%0 = tail call <4 x i8> @llvm.mips.repl.qb(i32 %a0)
|
||||
%1 = bitcast <4 x i8> %0 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
define { i32 } @test__builtin_mips_repl_ph1(i32 %i0) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: repl.ph
|
||||
|
||||
%0 = tail call <2 x i16> @llvm.mips.repl.ph(i32 0)
|
||||
%1 = bitcast <2 x i16> %0 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.mips.repl.ph(i32) nounwind readnone
|
||||
|
||||
define { i32 } @test__builtin_mips_repl_ph2(i32 %i0, i32 %a0) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: replv.ph
|
||||
|
||||
%0 = tail call <2 x i16> @llvm.mips.repl.ph(i32 %a0)
|
||||
%1 = bitcast <2 x i16> %0 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
define i32 @test__builtin_mips_bitrev1(i32 %i0, i32 %a0) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: bitrev
|
||||
|
||||
%0 = tail call i32 @llvm.mips.bitrev(i32 %a0)
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.mips.bitrev(i32) nounwind readnone
|
||||
|
||||
@ -323,3 +323,16 @@ entry:
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
define { i32 } @test__builtin_mips_absq_s_qb1(i32 %i0, i32 %a0.coerce) nounwind {
|
||||
entry:
|
||||
; CHECK: absq_s.qb
|
||||
|
||||
%0 = bitcast i32 %a0.coerce to <4 x i8>
|
||||
%1 = tail call <4 x i8> @llvm.mips.absq.s.qb(<4 x i8> %0)
|
||||
%2 = bitcast <4 x i8> %1 to i32
|
||||
%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
|
||||
ret { i32 } %.fca.0.insert
|
||||
}
|
||||
|
||||
declare <4 x i8> @llvm.mips.absq.s.qb(<4 x i8>) nounwind
|
||||
|
||||
Loading…
Reference in New Issue
Block a user