mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-02 17:55:18 +00:00
Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145927 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
34671b812a
commit
cb6bd11bd6
@ -5092,7 +5092,7 @@ let Constraints = "$src1 = $dst" in {
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/// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
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multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
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PatFrag mem_frag128, Intrinsic IntId128> {
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Intrinsic IntId128> {
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def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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@ -5104,12 +5104,12 @@ multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst,
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(IntId128
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(bitconvert (mem_frag128 addr:$src))))]>, OpSize;
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(bitconvert (memopv2i64 addr:$src))))]>, OpSize;
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}
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/// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
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multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
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PatFrag mem_frag256, Intrinsic IntId256> {
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Intrinsic IntId256> {
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def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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@ -5121,32 +5121,32 @@ multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst,
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(IntId256
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(bitconvert (mem_frag256 addr:$src))))]>, OpSize;
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(bitconvert (memopv4i64 addr:$src))))]>, OpSize;
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}
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let Predicates = [HasAVX] in {
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defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
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defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
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int_x86_ssse3_pabs_b_128>, VEX;
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defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
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defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
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int_x86_ssse3_pabs_w_128>, VEX;
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defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
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defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
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int_x86_ssse3_pabs_d_128>, VEX;
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}
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let Predicates = [HasAVX2] in {
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defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb", memopv32i8,
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defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
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int_x86_avx2_pabs_b>, VEX;
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defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw", memopv16i16,
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defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
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int_x86_avx2_pabs_w>, VEX;
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defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd", memopv8i32,
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defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
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int_x86_avx2_pabs_d>, VEX;
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}
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defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
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defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
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int_x86_ssse3_pabs_b_128>;
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defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
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defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
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int_x86_ssse3_pabs_w_128>;
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defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
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defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
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int_x86_ssse3_pabs_d_128>;
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//===---------------------------------------------------------------------===//
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@ -5155,8 +5155,7 @@ defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
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/// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
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multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
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PatFrag mem_frag128, Intrinsic IntId128,
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bit Is2Addr = 1> {
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Intrinsic IntId128, bit Is2Addr = 1> {
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let isCommutable = 1 in
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def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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@ -5172,11 +5171,11 @@ multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst,
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(IntId128 VR128:$src1,
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(bitconvert (mem_frag128 addr:$src2))))]>, OpSize;
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(bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
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}
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multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
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PatFrag mem_frag256, Intrinsic IntId256> {
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Intrinsic IntId256> {
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let isCommutable = 1 in
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def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2),
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@ -5188,94 +5187,94 @@ multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst,
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(IntId256 VR256:$src1,
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(bitconvert (mem_frag256 addr:$src2))))]>, OpSize;
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(bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
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}
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let ImmT = NoImm, Predicates = [HasAVX] in {
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let isCommutable = 0 in {
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defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
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defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw",
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int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
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defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
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defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd",
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int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
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defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
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defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
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int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
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defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
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defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw",
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int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
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defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
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defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd",
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int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
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defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
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defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
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int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
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defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
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defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
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int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
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defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
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defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb",
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int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
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defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
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defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb",
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int_x86_ssse3_psign_b_128, 0>, VEX_4V;
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defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
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defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw",
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int_x86_ssse3_psign_w_128, 0>, VEX_4V;
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defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
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defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd",
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int_x86_ssse3_psign_d_128, 0>, VEX_4V;
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}
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defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
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defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
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int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
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}
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let ImmT = NoImm, Predicates = [HasAVX2] in {
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let isCommutable = 0 in {
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defm VPHADDW : SS3I_binop_rm_int_y<0x01, "vphaddw", memopv16i16,
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defm VPHADDW : SS3I_binop_rm_int_y<0x01, "vphaddw",
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int_x86_avx2_phadd_w>, VEX_4V;
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defm VPHADDD : SS3I_binop_rm_int_y<0x02, "vphaddd", memopv8i32,
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defm VPHADDD : SS3I_binop_rm_int_y<0x02, "vphaddd",
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int_x86_avx2_phadd_d>, VEX_4V;
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defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw", memopv16i16,
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defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
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int_x86_avx2_phadd_sw>, VEX_4V;
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defm VPHSUBW : SS3I_binop_rm_int_y<0x05, "vphsubw", memopv16i16,
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defm VPHSUBW : SS3I_binop_rm_int_y<0x05, "vphsubw",
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int_x86_avx2_phsub_w>, VEX_4V;
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defm VPHSUBD : SS3I_binop_rm_int_y<0x06, "vphsubd", memopv8i32,
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defm VPHSUBD : SS3I_binop_rm_int_y<0x06, "vphsubd",
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int_x86_avx2_phsub_d>, VEX_4V;
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defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw", memopv16i16,
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defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
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int_x86_avx2_phsub_sw>, VEX_4V;
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defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw", memopv32i8,
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defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
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int_x86_avx2_pmadd_ub_sw>, VEX_4V;
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defm VPSHUFB : SS3I_binop_rm_int_y<0x00, "vpshufb", memopv32i8,
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defm VPSHUFB : SS3I_binop_rm_int_y<0x00, "vpshufb",
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int_x86_avx2_pshuf_b>, VEX_4V;
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defm VPSIGNB : SS3I_binop_rm_int_y<0x08, "vpsignb", memopv32i8,
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defm VPSIGNB : SS3I_binop_rm_int_y<0x08, "vpsignb",
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int_x86_avx2_psign_b>, VEX_4V;
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defm VPSIGNW : SS3I_binop_rm_int_y<0x09, "vpsignw", memopv16i16,
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defm VPSIGNW : SS3I_binop_rm_int_y<0x09, "vpsignw",
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int_x86_avx2_psign_w>, VEX_4V;
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defm VPSIGND : SS3I_binop_rm_int_y<0x0A, "vpsignd", memopv8i32,
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defm VPSIGND : SS3I_binop_rm_int_y<0x0A, "vpsignd",
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int_x86_avx2_psign_d>, VEX_4V;
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}
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defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw", memopv16i16,
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defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
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int_x86_avx2_pmul_hr_sw>, VEX_4V;
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}
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// None of these have i8 immediate fields.
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let ImmT = NoImm, Constraints = "$src1 = $dst" in {
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let isCommutable = 0 in {
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defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
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defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw",
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int_x86_ssse3_phadd_w_128>;
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defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
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defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd",
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int_x86_ssse3_phadd_d_128>;
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defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
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defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
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int_x86_ssse3_phadd_sw_128>;
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defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
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defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw",
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int_x86_ssse3_phsub_w_128>;
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defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
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defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd",
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int_x86_ssse3_phsub_d_128>;
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defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
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defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
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int_x86_ssse3_phsub_sw_128>;
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defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
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defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
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int_x86_ssse3_pmadd_ub_sw_128>;
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defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
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defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb",
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int_x86_ssse3_pshuf_b_128>;
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defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
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defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb",
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int_x86_ssse3_psign_b_128>;
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defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
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defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw",
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int_x86_ssse3_psign_w_128>;
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defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
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defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd",
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int_x86_ssse3_psign_d_128>;
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}
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defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
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defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
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int_x86_ssse3_pmul_hr_sw_128>;
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}
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@ -6202,7 +6201,7 @@ multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst,
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(IntId128
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(bitconvert (memopv8i16 addr:$src))))]>, OpSize;
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(bitconvert (memopv2i64 addr:$src))))]>, OpSize;
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}
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let Predicates = [HasAVX] in
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@ -6228,7 +6227,7 @@ multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst,
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(IntId128 VR128:$src1,
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(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
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(bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
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}
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/// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
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@ -6244,7 +6243,7 @@ multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst,
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(IntId256 VR256:$src1,
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(bitconvert (memopv32i8 addr:$src2))))]>, OpSize;
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(bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
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}
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let Predicates = [HasAVX] in {
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@ -7245,7 +7244,8 @@ multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
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def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop_i:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
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[(set RC:$dst, (IntVar RC:$src1,
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(bitconvert (i_frag addr:$src2))))]>, VEX_4V;
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def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, i8imm:$src2),
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@ -7259,11 +7259,11 @@ multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
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let ExeDomain = SSEPackedSingle in {
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defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
|
||||
memopv4f32, memopv4i32,
|
||||
memopv4f32, memopv2i64,
|
||||
int_x86_avx_vpermilvar_ps,
|
||||
int_x86_avx_vpermil_ps>;
|
||||
defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
|
||||
memopv8f32, memopv8i32,
|
||||
memopv8f32, memopv4i64,
|
||||
int_x86_avx_vpermilvar_ps_256,
|
||||
int_x86_avx_vpermil_ps_256>;
|
||||
}
|
||||
@ -7494,11 +7494,12 @@ multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
|
||||
(ins VR256:$src1, i256mem:$src2),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
[(set VR256:$dst, (Int VR256:$src1, (mem_frag addr:$src2)))]>,
|
||||
[(set VR256:$dst, (Int VR256:$src1,
|
||||
(bitconvert (mem_frag addr:$src2))))]>,
|
||||
VEX_4V;
|
||||
}
|
||||
|
||||
defm VPERMD : avx2_perm<0x36, "vpermd", memopv8i32, int_x86_avx2_permd>;
|
||||
defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, int_x86_avx2_permd>;
|
||||
let ExeDomain = SSEPackedSingle in
|
||||
defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, int_x86_avx2_permps>;
|
||||
|
||||
|
||||
@ -2333,6 +2333,12 @@ define <4 x float> @test_x86_avx_vpermilvar_ps(<4 x float> %a0, <4 x i32> %a1) {
|
||||
%res = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> %a1) ; <<4 x float>> [#uses=1]
|
||||
ret <4 x float> %res
|
||||
}
|
||||
define <4 x float> @test_x86_avx_vpermilvar_ps_load(<4 x float> %a0, <4 x i32>* %a1) {
|
||||
; CHECK: vpermilps
|
||||
%a2 = load <4 x i32>* %a1
|
||||
%res = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> %a2) ; <<4 x float>> [#uses=1]
|
||||
ret <4 x float> %res
|
||||
}
|
||||
declare <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float>, <4 x i32>) nounwind readnone
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user