mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-24 09:29:42 +00:00
ARM64: remove duplication by templating InstPrinter methods
No functional change, so no tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207638 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
00bdeb4c54
commit
cb87e23ce2
@ -191,7 +191,7 @@ def SImm7s4Operand : AsmOperandClass {
|
||||
}
|
||||
def simm7s4 : Operand<i32> {
|
||||
let ParserMatchClass = SImm7s4Operand;
|
||||
let PrintMethod = "printImmScale4";
|
||||
let PrintMethod = "printImmScale<4>";
|
||||
}
|
||||
|
||||
// simm7s8 predicate - True if the immediate is a multiple of 8 in the range
|
||||
@ -202,7 +202,7 @@ def SImm7s8Operand : AsmOperandClass {
|
||||
}
|
||||
def simm7s8 : Operand<i32> {
|
||||
let ParserMatchClass = SImm7s8Operand;
|
||||
let PrintMethod = "printImmScale8";
|
||||
let PrintMethod = "printImmScale<8>";
|
||||
}
|
||||
|
||||
// simm7s16 predicate - True if the immediate is a multiple of 16 in the range
|
||||
@ -213,7 +213,7 @@ def SImm7s16Operand : AsmOperandClass {
|
||||
}
|
||||
def simm7s16 : Operand<i32> {
|
||||
let ParserMatchClass = SImm7s16Operand;
|
||||
let PrintMethod = "printImmScale16";
|
||||
let PrintMethod = "printImmScale<16>";
|
||||
}
|
||||
|
||||
// imm0_65535 predicate - True if the immediate is in the range [0,65535].
|
||||
@ -2012,7 +2012,7 @@ def MemoryIndexed8Operand : AsmOperandClass {
|
||||
}
|
||||
def am_indexed8 : Operand<i64>,
|
||||
ComplexPattern<i64, 2, "SelectAddrModeIndexed8", []> {
|
||||
let PrintMethod = "printAMIndexed8";
|
||||
let PrintMethod = "printAMIndexed<8>";
|
||||
let EncoderMethod
|
||||
= "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale1>";
|
||||
let ParserMatchClass = MemoryIndexed8Operand;
|
||||
@ -2027,7 +2027,7 @@ def MemoryIndexed16Operand : AsmOperandClass {
|
||||
}
|
||||
def am_indexed16 : Operand<i64>,
|
||||
ComplexPattern<i64, 2, "SelectAddrModeIndexed16", []> {
|
||||
let PrintMethod = "printAMIndexed16";
|
||||
let PrintMethod = "printAMIndexed<16>";
|
||||
let EncoderMethod
|
||||
= "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale2>";
|
||||
let ParserMatchClass = MemoryIndexed16Operand;
|
||||
@ -2042,7 +2042,7 @@ def MemoryIndexed32Operand : AsmOperandClass {
|
||||
}
|
||||
def am_indexed32 : Operand<i64>,
|
||||
ComplexPattern<i64, 2, "SelectAddrModeIndexed32", []> {
|
||||
let PrintMethod = "printAMIndexed32";
|
||||
let PrintMethod = "printAMIndexed<32>";
|
||||
let EncoderMethod
|
||||
= "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale4>";
|
||||
let ParserMatchClass = MemoryIndexed32Operand;
|
||||
@ -2057,7 +2057,7 @@ def MemoryIndexed64Operand : AsmOperandClass {
|
||||
}
|
||||
def am_indexed64 : Operand<i64>,
|
||||
ComplexPattern<i64, 2, "SelectAddrModeIndexed64", []> {
|
||||
let PrintMethod = "printAMIndexed64";
|
||||
let PrintMethod = "printAMIndexed<64>";
|
||||
let EncoderMethod
|
||||
= "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale8>";
|
||||
let ParserMatchClass = MemoryIndexed64Operand;
|
||||
@ -2072,7 +2072,7 @@ def MemoryIndexed128Operand : AsmOperandClass {
|
||||
}
|
||||
def am_indexed128 : Operand<i64>,
|
||||
ComplexPattern<i64, 2, "SelectAddrModeIndexed128", []> {
|
||||
let PrintMethod = "printAMIndexed128";
|
||||
let PrintMethod = "printAMIndexed<128>";
|
||||
let EncoderMethod
|
||||
= "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale16>";
|
||||
let ParserMatchClass = MemoryIndexed128Operand;
|
||||
@ -2196,7 +2196,7 @@ def MemROAsmOperand64 : MemROAsmOperand<64>;
|
||||
def MemROAsmOperand128 : MemROAsmOperand<128>;
|
||||
|
||||
class ro_indexed<int sz> : Operand<i64> { // ComplexPattern<...>
|
||||
let PrintMethod = "printMemoryRegOffset"#sz;
|
||||
let PrintMethod = "printMemoryRegOffset<" # sz # ">";
|
||||
let MIOperandInfo = (ops GPR64sp:$base, GPR64:$offset, i32imm:$extend);
|
||||
}
|
||||
|
||||
@ -2464,12 +2464,12 @@ def MemoryUnscaledOperand : AsmOperandClass {
|
||||
let DiagnosticType = "InvalidMemoryIndexedSImm9";
|
||||
}
|
||||
class am_unscaled_operand : Operand<i64> {
|
||||
let PrintMethod = "printAMUnscaled";
|
||||
let PrintMethod = "printAMIndexed<8>";
|
||||
let ParserMatchClass = MemoryUnscaledOperand;
|
||||
let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
|
||||
}
|
||||
class am_unscaled_wb_operand : Operand<i64> {
|
||||
let PrintMethod = "printAMUnscaledWB";
|
||||
let PrintMethod = "printAMIndexedWB<8>";
|
||||
let ParserMatchClass = MemoryUnscaledOperand;
|
||||
let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
|
||||
}
|
||||
@ -2791,12 +2791,12 @@ def MemoryIndexed32SImm7 : AsmOperandClass {
|
||||
let DiagnosticType = "InvalidMemoryIndexed32SImm7";
|
||||
}
|
||||
def am_indexed32simm7 : Operand<i32> { // ComplexPattern<...>
|
||||
let PrintMethod = "printAMIndexed32";
|
||||
let PrintMethod = "printAMIndexed<32>";
|
||||
let ParserMatchClass = MemoryIndexed32SImm7;
|
||||
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
|
||||
}
|
||||
def am_indexed32simm7_wb : Operand<i32> { // ComplexPattern<...>
|
||||
let PrintMethod = "printAMIndexed32WB";
|
||||
let PrintMethod = "printAMIndexedWB<32>";
|
||||
let ParserMatchClass = MemoryIndexed32SImm7;
|
||||
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
|
||||
}
|
||||
@ -2806,12 +2806,12 @@ def MemoryIndexed64SImm7 : AsmOperandClass {
|
||||
let DiagnosticType = "InvalidMemoryIndexed64SImm7";
|
||||
}
|
||||
def am_indexed64simm7 : Operand<i32> { // ComplexPattern<...>
|
||||
let PrintMethod = "printAMIndexed64";
|
||||
let PrintMethod = "printAMIndexed<64>";
|
||||
let ParserMatchClass = MemoryIndexed64SImm7;
|
||||
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
|
||||
}
|
||||
def am_indexed64simm7_wb : Operand<i32> { // ComplexPattern<...>
|
||||
let PrintMethod = "printAMIndexed64WB";
|
||||
let PrintMethod = "printAMIndexedWB<64>";
|
||||
let ParserMatchClass = MemoryIndexed64SImm7;
|
||||
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
|
||||
}
|
||||
@ -2821,12 +2821,12 @@ def MemoryIndexed128SImm7 : AsmOperandClass {
|
||||
let DiagnosticType = "InvalidMemoryIndexed128SImm7";
|
||||
}
|
||||
def am_indexed128simm7 : Operand<i32> { // ComplexPattern<...>
|
||||
let PrintMethod = "printAMIndexed128";
|
||||
let PrintMethod = "printAMIndexed<128>";
|
||||
let ParserMatchClass = MemoryIndexed128SImm7;
|
||||
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
|
||||
}
|
||||
def am_indexed128simm7_wb : Operand<i32> { // ComplexPattern<...>
|
||||
let PrintMethod = "printAMIndexed128WB";
|
||||
let PrintMethod = "printAMIndexedWB<128>";
|
||||
let ParserMatchClass = MemoryIndexed128SImm7;
|
||||
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
|
||||
}
|
||||
|
||||
@ -167,18 +167,18 @@ def tcGPR64 : RegisterClass<"ARM64", [i64], 64, (sub GPR64common, X19, X20, X21,
|
||||
// GPR register classes for post increment amount of vector load/store that
|
||||
// has alternate printing when Rm=31 and prints a constant immediate value
|
||||
// equal to the total number of bytes transferred.
|
||||
def GPR64pi1 : RegisterOperand<GPR64, "printPostIncOperand1">;
|
||||
def GPR64pi2 : RegisterOperand<GPR64, "printPostIncOperand2">;
|
||||
def GPR64pi3 : RegisterOperand<GPR64, "printPostIncOperand3">;
|
||||
def GPR64pi4 : RegisterOperand<GPR64, "printPostIncOperand4">;
|
||||
def GPR64pi6 : RegisterOperand<GPR64, "printPostIncOperand6">;
|
||||
def GPR64pi8 : RegisterOperand<GPR64, "printPostIncOperand8">;
|
||||
def GPR64pi12 : RegisterOperand<GPR64, "printPostIncOperand12">;
|
||||
def GPR64pi16 : RegisterOperand<GPR64, "printPostIncOperand16">;
|
||||
def GPR64pi24 : RegisterOperand<GPR64, "printPostIncOperand24">;
|
||||
def GPR64pi32 : RegisterOperand<GPR64, "printPostIncOperand32">;
|
||||
def GPR64pi48 : RegisterOperand<GPR64, "printPostIncOperand48">;
|
||||
def GPR64pi64 : RegisterOperand<GPR64, "printPostIncOperand64">;
|
||||
def GPR64pi1 : RegisterOperand<GPR64, "printPostIncOperand<1>">;
|
||||
def GPR64pi2 : RegisterOperand<GPR64, "printPostIncOperand<2>">;
|
||||
def GPR64pi3 : RegisterOperand<GPR64, "printPostIncOperand<3>">;
|
||||
def GPR64pi4 : RegisterOperand<GPR64, "printPostIncOperand<4>">;
|
||||
def GPR64pi6 : RegisterOperand<GPR64, "printPostIncOperand<6>">;
|
||||
def GPR64pi8 : RegisterOperand<GPR64, "printPostIncOperand<8>">;
|
||||
def GPR64pi12 : RegisterOperand<GPR64, "printPostIncOperand<12>">;
|
||||
def GPR64pi16 : RegisterOperand<GPR64, "printPostIncOperand<16>">;
|
||||
def GPR64pi24 : RegisterOperand<GPR64, "printPostIncOperand<24>">;
|
||||
def GPR64pi32 : RegisterOperand<GPR64, "printPostIncOperand<32>">;
|
||||
def GPR64pi48 : RegisterOperand<GPR64, "printPostIncOperand<48>">;
|
||||
def GPR64pi64 : RegisterOperand<GPR64, "printPostIncOperand<64>">;
|
||||
|
||||
// Condition code regclass.
|
||||
def CCR : RegisterClass<"ARM64", [i32], 32, (add CPSR)> {
|
||||
|
||||
@ -1027,66 +1027,6 @@ void ARM64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
|
||||
assert(0 && "unknown operand kind in printPostIncOperand64");
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printPostIncOperand1(const MCInst *MI, unsigned OpNo,
|
||||
raw_ostream &O) {
|
||||
printPostIncOperand(MI, OpNo, 1, O);
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printPostIncOperand2(const MCInst *MI, unsigned OpNo,
|
||||
raw_ostream &O) {
|
||||
printPostIncOperand(MI, OpNo, 2, O);
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printPostIncOperand3(const MCInst *MI, unsigned OpNo,
|
||||
raw_ostream &O) {
|
||||
printPostIncOperand(MI, OpNo, 3, O);
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printPostIncOperand4(const MCInst *MI, unsigned OpNo,
|
||||
raw_ostream &O) {
|
||||
printPostIncOperand(MI, OpNo, 4, O);
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printPostIncOperand6(const MCInst *MI, unsigned OpNo,
|
||||
raw_ostream &O) {
|
||||
printPostIncOperand(MI, OpNo, 6, O);
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printPostIncOperand8(const MCInst *MI, unsigned OpNo,
|
||||
raw_ostream &O) {
|
||||
printPostIncOperand(MI, OpNo, 8, O);
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printPostIncOperand12(const MCInst *MI, unsigned OpNo,
|
||||
raw_ostream &O) {
|
||||
printPostIncOperand(MI, OpNo, 12, O);
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printPostIncOperand16(const MCInst *MI, unsigned OpNo,
|
||||
raw_ostream &O) {
|
||||
printPostIncOperand(MI, OpNo, 16, O);
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printPostIncOperand24(const MCInst *MI, unsigned OpNo,
|
||||
raw_ostream &O) {
|
||||
printPostIncOperand(MI, OpNo, 24, O);
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printPostIncOperand32(const MCInst *MI, unsigned OpNo,
|
||||
raw_ostream &O) {
|
||||
printPostIncOperand(MI, OpNo, 32, O);
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printPostIncOperand48(const MCInst *MI, unsigned OpNo,
|
||||
raw_ostream &O) {
|
||||
printPostIncOperand(MI, OpNo, 48, O);
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printPostIncOperand64(const MCInst *MI, unsigned OpNo,
|
||||
raw_ostream &O) {
|
||||
printPostIncOperand(MI, OpNo, 64, O);
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
|
||||
raw_ostream &O) {
|
||||
const MCOperand &Op = MI->getOperand(OpNo);
|
||||
@ -1203,19 +1143,10 @@ void ARM64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
|
||||
O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printImmScale4(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
O << '#' << 4 * MI->getOperand(OpNum).getImm();
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printImmScale8(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
O << '#' << 8 * MI->getOperand(OpNum).getImm();
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printImmScale16(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
O << '#' << 16 * MI->getOperand(OpNum).getImm();
|
||||
template<int Scale>
|
||||
void ARM64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
O << '#' << Scale * MI->getOperand(OpNum).getImm();
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printAMIndexed(const MCInst *MI, unsigned OpNum,
|
||||
@ -1256,35 +1187,14 @@ void ARM64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
|
||||
O << '#' << prfop;
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printMemoryPostIndexed32(const MCInst *MI,
|
||||
unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']' << ", #"
|
||||
<< 4 * MI->getOperand(OpNum + 1).getImm();
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printMemoryPostIndexed64(const MCInst *MI,
|
||||
unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']' << ", #"
|
||||
<< 8 * MI->getOperand(OpNum + 1).getImm();
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printMemoryPostIndexed128(const MCInst *MI,
|
||||
unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']' << ", #"
|
||||
<< 16 * MI->getOperand(OpNum + 1).getImm();
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printMemoryPostIndexed(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
raw_ostream &O, unsigned Scale) {
|
||||
O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']' << ", #"
|
||||
<< MI->getOperand(OpNum + 1).getImm();
|
||||
<< Scale * MI->getOperand(OpNum + 1).getImm();
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printMemoryRegOffset(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O, int LegalShiftAmt) {
|
||||
raw_ostream &O, int Scale) {
|
||||
unsigned Val = MI->getOperand(OpNum + 2).getImm();
|
||||
ARM64_AM::ExtendType ExtType = ARM64_AM::getMemExtendType(Val);
|
||||
|
||||
@ -1303,36 +1213,11 @@ void ARM64InstPrinter::printMemoryRegOffset(const MCInst *MI, unsigned OpNum,
|
||||
O << ", " << ARM64_AM::getExtendName(ExtType);
|
||||
|
||||
if (DoShift)
|
||||
O << " #" << LegalShiftAmt;
|
||||
O << " #" << Log2_32(Scale);
|
||||
|
||||
O << "]";
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printMemoryRegOffset8(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
printMemoryRegOffset(MI, OpNum, O, 0);
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printMemoryRegOffset16(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
printMemoryRegOffset(MI, OpNum, O, 1);
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printMemoryRegOffset32(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
printMemoryRegOffset(MI, OpNum, O, 2);
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printMemoryRegOffset64(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
printMemoryRegOffset(MI, OpNum, O, 3);
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printMemoryRegOffset128(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
printMemoryRegOffset(MI, OpNum, O, 4);
|
||||
}
|
||||
|
||||
void ARM64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
const MCOperand &MO = MI->getOperand(OpNum);
|
||||
|
||||
@ -47,18 +47,11 @@ protected:
|
||||
void printHexImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
|
||||
raw_ostream &O);
|
||||
void printPostIncOperand1(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printPostIncOperand2(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printPostIncOperand3(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printPostIncOperand4(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printPostIncOperand6(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printPostIncOperand8(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printPostIncOperand12(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printPostIncOperand16(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printPostIncOperand24(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printPostIncOperand32(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printPostIncOperand48(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printPostIncOperand64(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
template<int Amount>
|
||||
void printPostIncOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
|
||||
printPostIncOperand(MI, OpNo, Amount, O);
|
||||
}
|
||||
|
||||
void printVRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printSysCROperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printAddSubImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
@ -75,66 +68,38 @@ protected:
|
||||
raw_ostream &O);
|
||||
void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale,
|
||||
raw_ostream &O);
|
||||
void printAMIndexed128(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
|
||||
printAMIndexed(MI, OpNum, 16, O);
|
||||
}
|
||||
void printAMIndexed128WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
|
||||
printAMIndexedWB(MI, OpNum, 16, O);
|
||||
|
||||
template<int BitWidth>
|
||||
void printAMIndexed(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
|
||||
printAMIndexed(MI, OpNum, BitWidth / 8, O);
|
||||
}
|
||||
|
||||
void printAMIndexed64(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
|
||||
printAMIndexed(MI, OpNum, 8, O);
|
||||
}
|
||||
void printAMIndexed64WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
|
||||
printAMIndexedWB(MI, OpNum, 8, O);
|
||||
template<int BitWidth>
|
||||
void printAMIndexedWB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
|
||||
printAMIndexedWB(MI, OpNum, BitWidth / 8, O);
|
||||
}
|
||||
|
||||
void printAMIndexed32(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
|
||||
printAMIndexed(MI, OpNum, 4, O);
|
||||
}
|
||||
void printAMIndexed32WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
|
||||
printAMIndexedWB(MI, OpNum, 4, O);
|
||||
}
|
||||
|
||||
void printAMIndexed16(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
|
||||
printAMIndexed(MI, OpNum, 2, O);
|
||||
}
|
||||
void printAMIndexed16WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
|
||||
printAMIndexedWB(MI, OpNum, 2, O);
|
||||
}
|
||||
|
||||
void printAMIndexed8(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
|
||||
printAMIndexed(MI, OpNum, 1, O);
|
||||
}
|
||||
void printAMIndexed8WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
|
||||
printAMIndexedWB(MI, OpNum, 1, O);
|
||||
}
|
||||
void printAMUnscaled(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
|
||||
printAMIndexed(MI, OpNum, 1, O);
|
||||
}
|
||||
void printAMUnscaledWB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
|
||||
printAMIndexedWB(MI, OpNum, 1, O);
|
||||
}
|
||||
void printAMNoIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printImmScale4(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printImmScale8(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printImmScale16(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
|
||||
template<int Scale>
|
||||
void printImmScale(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
|
||||
void printPrefetchOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printMemoryPostIndexed(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printMemoryPostIndexed32(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O);
|
||||
void printMemoryPostIndexed64(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O);
|
||||
void printMemoryPostIndexed128(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O);
|
||||
|
||||
void printMemoryPostIndexed(const MCInst *MI, unsigned OpNum, raw_ostream &O,
|
||||
unsigned Scale);
|
||||
template<int BitWidth>
|
||||
void printMemoryPostIndexed(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O) {
|
||||
printMemoryPostIndexed(MI, OpNum, O, BitWidth / 8);
|
||||
}
|
||||
|
||||
void printMemoryRegOffset(const MCInst *MI, unsigned OpNum, raw_ostream &O,
|
||||
int LegalShiftAmt);
|
||||
void printMemoryRegOffset8(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printMemoryRegOffset16(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printMemoryRegOffset32(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printMemoryRegOffset64(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
void printMemoryRegOffset128(const MCInst *MI, unsigned OpNum,
|
||||
raw_ostream &O);
|
||||
template<int BitWidth>
|
||||
void printMemoryRegOffset(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
|
||||
printMemoryRegOffset(MI, OpNum, O, BitWidth / 8);
|
||||
}
|
||||
|
||||
void printFPImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user