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Add ori reg, reg, 0 as a move instruction. This can be generated from

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loading a 32bit constant into a register whose low halfword is all zeroes.

We now omit the ori after the lis for the following C code:

int bar(int y) { return y * 0x00F0000; }

_bar:
.LBB_bar_0:     ; entry
        ; IMPLICIT_DEF
        lis r2, 15
        mullw r3, r3, r2
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16825 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2004-10-07 22:26:12 +00:00
parent 5a181c848b
commit cb90de37a7
1 changed files with 11 additions and 0 deletions
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11
lib/Target/PowerPC/PPCInstrInfo.cpp
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@ -46,6 +46,17 @@ bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI,
destReg = MI.getOperand(0).getReg();
return true;
}
} else if (oc == PPC::ORI) { // ori r1, r2, 0
assert(MI.getNumOperands() == 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
MI.getOperand(2).isImmediate() &&
"invalid PPC ORI instruction!");
if (MI.getOperand(2).getImmedValue()==0) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
}
} else if (oc == PPC::FMR) { // fmr r1, r2
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&