mirror of
https://github.com/c64scene-ar/llvm-6502.git
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[FastISel][AArch64] Add select folding support for the XALU intrinsics.
This improves the code generation for the XALU intrinsics when the condition is feeding a select instruction. This also updates and enables the XALU unit tests for FastISel. This fixes <rdar://problem/17831117>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214350 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
parent
29c424cb12
commit
cb99212bc1
@ -1052,54 +1052,56 @@ bool AArch64FastISel::SelectSelect(const Instruction *I) {
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DestVT != MVT::f64)
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return false;
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unsigned CondReg = getRegForValue(SI->getCondition());
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if (CondReg == 0)
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return false;
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unsigned TrueReg = getRegForValue(SI->getTrueValue());
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if (TrueReg == 0)
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return false;
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unsigned FalseReg = getRegForValue(SI->getFalseValue());
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if (FalseReg == 0)
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return false;
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unsigned SelectOpc;
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switch (DestVT.SimpleTy) {
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default: return false;
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case MVT::i32: SelectOpc = AArch64::CSELWr; break;
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case MVT::i64: SelectOpc = AArch64::CSELXr; break;
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case MVT::f32: SelectOpc = AArch64::FCSELSrrr; break;
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case MVT::f64: SelectOpc = AArch64::FCSELDrrr; break;
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}
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const Value *Cond = SI->getCondition();
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bool NeedTest = true;
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AArch64CC::CondCode CC = AArch64CC::NE;
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if (foldXALUIntrinsic(CC, I, Cond))
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NeedTest = false;
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MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass);
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unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
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ANDReg)
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.addReg(CondReg)
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unsigned CondReg = getRegForValue(Cond);
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if (!CondReg)
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return false;
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bool CondIsKill = hasTrivialKill(Cond);
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if (NeedTest) {
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MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass);
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unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
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ANDReg)
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.addReg(CondReg, getKillRegState(CondIsKill))
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.addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SUBSWri))
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SUBSWri))
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.addReg(ANDReg)
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.addReg(ANDReg)
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.addImm(0)
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.addImm(0);
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unsigned SelectOpc;
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switch (DestVT.SimpleTy) {
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default:
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return false;
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case MVT::i32:
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SelectOpc = AArch64::CSELWr;
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break;
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case MVT::i64:
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SelectOpc = AArch64::CSELXr;
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break;
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case MVT::f32:
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SelectOpc = AArch64::FCSELSrrr;
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break;
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case MVT::f64:
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SelectOpc = AArch64::FCSELDrrr;
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break;
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}
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unsigned TrueReg = getRegForValue(SI->getTrueValue());
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bool TrueIsKill = hasTrivialKill(SI->getTrueValue());
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unsigned FalseReg = getRegForValue(SI->getFalseValue());
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bool FalseIsKill = hasTrivialKill(SI->getFalseValue());
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if (!TrueReg || !FalseReg)
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return false;
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unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SelectOpc),
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ResultReg)
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.addReg(TrueReg)
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.addReg(FalseReg)
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.addImm(AArch64CC::NE);
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.addReg(TrueReg, getKillRegState(TrueIsKill))
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.addReg(FalseReg, getKillRegState(FalseIsKill))
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.addImm(CC);
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UpdateValueMap(I, ResultReg);
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return true;
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@ -1,13 +1,14 @@
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; RUN: llc < %s -march=arm64 -aarch64-atomic-cfg-tidy=0 | FileCheck %s
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; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 < %s | FileCheck %s
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; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort < %s | FileCheck %s
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;
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; Get the actual value of the overflow bit.
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;
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define i1 @saddo.i32(i32 %v1, i32 %v2, i32* %res) {
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define zeroext i1 @saddo.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; CHECK-LABEL: saddo.i32
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; CHECK: adds w8, w0, w1
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; CHECK-NEXT: cset w0, vs
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; CHECK: adds {{w[0-9]+}}, w0, w1
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; CHECK-NEXT: cset {{w[0-9]+}}, vs
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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@ -15,11 +16,11 @@ entry:
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ret i1 %obit
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}
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define i1 @saddo.i64(i64 %v1, i64 %v2, i64* %res) {
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define zeroext i1 @saddo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; CHECK-LABEL: saddo.i64
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; CHECK: adds x8, x0, x1
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; CHECK-NEXT: cset w0, vs
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; CHECK: adds {{x[0-9]+}}, x0, x1
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; CHECK-NEXT: cset {{w[0-9]+}}, vs
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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@ -27,11 +28,11 @@ entry:
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ret i1 %obit
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}
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define i1 @uaddo.i32(i32 %v1, i32 %v2, i32* %res) {
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define zeroext i1 @uaddo.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; CHECK-LABEL: uaddo.i32
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; CHECK: adds w8, w0, w1
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; CHECK-NEXT: cset w0, hs
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; CHECK: adds {{w[0-9]+}}, w0, w1
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; CHECK-NEXT: cset {{w[0-9]+}}, hs
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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@ -39,11 +40,11 @@ entry:
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ret i1 %obit
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}
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define i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
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define zeroext i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; CHECK-LABEL: uaddo.i64
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; CHECK: adds x8, x0, x1
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; CHECK-NEXT: cset w0, hs
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; CHECK: adds {{x[0-9]+}}, x0, x1
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; CHECK-NEXT: cset {{w[0-9]+}}, hs
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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@ -51,11 +52,11 @@ entry:
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ret i1 %obit
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}
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define i1 @ssubo.i32(i32 %v1, i32 %v2, i32* %res) {
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define zeroext i1 @ssubo.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; CHECK-LABEL: ssubo.i32
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; CHECK: subs w8, w0, w1
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; CHECK-NEXT: cset w0, vs
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; CHECK: subs {{w[0-9]+}}, w0, w1
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; CHECK-NEXT: cset {{w[0-9]+}}, vs
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%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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@ -63,11 +64,11 @@ entry:
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ret i1 %obit
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}
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define i1 @ssubo.i64(i64 %v1, i64 %v2, i64* %res) {
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define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; CHECK-LABEL: ssubo.i64
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; CHECK: subs x8, x0, x1
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; CHECK-NEXT: cset w0, vs
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; CHECK: subs {{x[0-9]+}}, x0, x1
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; CHECK-NEXT: cset {{w[0-9]+}}, vs
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%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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@ -75,11 +76,11 @@ entry:
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ret i1 %obit
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}
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define i1 @usubo.i32(i32 %v1, i32 %v2, i32* %res) {
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define zeroext i1 @usubo.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; CHECK-LABEL: usubo.i32
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; CHECK: subs w8, w0, w1
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; CHECK-NEXT: cset w0, lo
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; CHECK: subs {{w[0-9]+}}, w0, w1
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; CHECK-NEXT: cset {{w[0-9]+}}, lo
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%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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@ -87,11 +88,11 @@ entry:
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ret i1 %obit
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}
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define i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
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define zeroext i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; CHECK-LABEL: usubo.i64
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; CHECK: subs x8, x0, x1
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; CHECK-NEXT: cset w0, lo
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; CHECK: subs {{x[0-9]+}}, x0, x1
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; CHECK-NEXT: cset {{w[0-9]+}}, lo
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%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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@ -99,13 +100,13 @@ entry:
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ret i1 %obit
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}
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define i1 @smulo.i32(i32 %v1, i32 %v2, i32* %res) {
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define zeroext i1 @smulo.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; CHECK-LABEL: smulo.i32
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; CHECK: smull x8, w0, w1
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; CHECK-NEXT: lsr x9, x8, #32
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; CHECK-NEXT: cmp w9, w8, asr #31
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; CHECK-NEXT: cset w0, ne
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; CHECK: smull x[[MREG:[0-9]+]], w0, w1
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; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x[[MREG]], #32
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; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
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; CHECK-NEXT: cset {{w[0-9]+}}, ne
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%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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@ -113,13 +114,13 @@ entry:
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ret i1 %obit
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}
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define i1 @smulo.i64(i64 %v1, i64 %v2, i64* %res) {
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define zeroext i1 @smulo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; CHECK-LABEL: smulo.i64
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; CHECK: mul x8, x0, x1
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; CHECK-NEXT: smulh x9, x0, x1
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; CHECK-NEXT: cmp x9, x8, asr #63
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; CHECK-NEXT: cset w0, ne
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; CHECK: mul [[MREG:x[0-9]+]], x0, x1
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; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
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; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
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; CHECK-NEXT: cset {{w[0-9]+}}, ne
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%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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@ -127,12 +128,12 @@ entry:
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ret i1 %obit
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}
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define i1 @umulo.i32(i32 %v1, i32 %v2, i32* %res) {
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define zeroext i1 @umulo.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; CHECK-LABEL: umulo.i32
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; CHECK: umull x8, w0, w1
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; CHECK-NEXT: cmp xzr, x8, lsr #32
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; CHECK-NEXT: cset w0, ne
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; CHECK: umull [[MREG:x[0-9]+]], w0, w1
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; CHECK-NEXT: cmp xzr, [[MREG]], lsr #32
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; CHECK-NEXT: cset {{w[0-9]+}}, ne
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%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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@ -140,13 +141,12 @@ entry:
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ret i1 %obit
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}
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define i1 @umulo.i64(i64 %v1, i64 %v2, i64* %res) {
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define zeroext i1 @umulo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; CHECK-LABEL: umulo.i64
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; CHECK: umulh x8, x0, x1
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; CHECK-NEXT: cmp xzr, x8
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; CHECK-NEXT: cset w8, ne
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; CHECK-NEXT: mul x9, x0, x1
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; CHECK: umulh [[MREG:x[0-9]+]], x0, x1
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; CHECK-NEXT: cmp xzr, [[MREG]]
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; CHECK-NEXT: cset {{w[0-9]+}}, ne
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%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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@ -249,9 +249,9 @@ entry:
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define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
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entry:
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; CHECK-LABEL: smulo.select.i32
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; CHECK: smull x8, w0, w1
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; CHECK-NEXT: lsr x9, x8, #32
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; CHECK-NEXT: cmp w9, w8, asr #31
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; CHECK: smull x[[MREG:[0-9]+]], w0, w1
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; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x[[MREG]], #32
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; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
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; CHECK-NEXT: csel w0, w0, w1, ne
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%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
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%obit = extractvalue {i32, i1} %t, 1
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@ -262,9 +262,9 @@ entry:
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define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
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entry:
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; CHECK-LABEL: smulo.select.i64
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; CHECK: mul x8, x0, x1
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; CHECK-NEXT: smulh x9, x0, x1
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; CHECK-NEXT: cmp x9, x8, asr #63
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; CHECK: mul [[MREG:x[0-9]+]], x0, x1
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; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
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; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
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; CHECK-NEXT: csel x0, x0, x1, ne
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%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
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%obit = extractvalue {i64, i1} %t, 1
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@ -275,8 +275,8 @@ entry:
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define i32 @umulo.select.i32(i32 %v1, i32 %v2) {
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entry:
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; CHECK-LABEL: umulo.select.i32
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; CHECK: umull x8, w0, w1
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; CHECK-NEXT: cmp xzr, x8, lsr #32
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; CHECK: umull [[MREG:x[0-9]+]], w0, w1
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; CHECK-NEXT: cmp xzr, [[MREG]], lsr #32
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; CHECK-NEXT: csel w0, w0, w1, ne
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%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
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%obit = extractvalue {i32, i1} %t, 1
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@ -287,8 +287,8 @@ entry:
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define i64 @umulo.select.i64(i64 %v1, i64 %v2) {
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entry:
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; CHECK-LABEL: umulo.select.i64
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; CHECK: umulh x8, x0, x1
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; CHECK-NEXT: cmp xzr, x8
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; CHECK: umulh [[MREG:x[0-9]+]], x0, x1
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; CHECK-NEXT: cmp xzr, [[MREG]]
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; CHECK-NEXT: csel x0, x0, x1, ne
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%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
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%obit = extractvalue {i64, i1} %t, 1
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@ -300,7 +300,7 @@ entry:
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;
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; Check the use of the overflow bit in combination with a branch instruction.
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;
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define i1 @saddo.br.i32(i32 %v1, i32 %v2) {
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define zeroext i1 @saddo.br.i32(i32 %v1, i32 %v2) {
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entry:
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; CHECK-LABEL: saddo.br.i32
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; CHECK: cmn w0, w1
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@ -317,7 +317,7 @@ continue:
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ret i1 true
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}
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|
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define i1 @saddo.br.i64(i64 %v1, i64 %v2) {
|
||||
define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
|
||||
entry:
|
||||
; CHECK-LABEL: saddo.br.i64
|
||||
; CHECK: cmn x0, x1
|
||||
@ -334,7 +334,7 @@ continue:
|
||||
ret i1 true
|
||||
}
|
||||
|
||||
define i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
|
||||
define zeroext i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
|
||||
entry:
|
||||
; CHECK-LABEL: uaddo.br.i32
|
||||
; CHECK: cmn w0, w1
|
||||
@ -351,7 +351,7 @@ continue:
|
||||
ret i1 true
|
||||
}
|
||||
|
||||
define i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
|
||||
define zeroext i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
|
||||
entry:
|
||||
; CHECK-LABEL: uaddo.br.i64
|
||||
; CHECK: cmn x0, x1
|
||||
@ -368,7 +368,7 @@ continue:
|
||||
ret i1 true
|
||||
}
|
||||
|
||||
define i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
|
||||
define zeroext i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
|
||||
entry:
|
||||
; CHECK-LABEL: ssubo.br.i32
|
||||
; CHECK: cmp w0, w1
|
||||
@ -385,7 +385,7 @@ continue:
|
||||
ret i1 true
|
||||
}
|
||||
|
||||
define i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
|
||||
define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
|
||||
entry:
|
||||
; CHECK-LABEL: ssubo.br.i64
|
||||
; CHECK: cmp x0, x1
|
||||
@ -402,7 +402,7 @@ continue:
|
||||
ret i1 true
|
||||
}
|
||||
|
||||
define i1 @usubo.br.i32(i32 %v1, i32 %v2) {
|
||||
define zeroext i1 @usubo.br.i32(i32 %v1, i32 %v2) {
|
||||
entry:
|
||||
; CHECK-LABEL: usubo.br.i32
|
||||
; CHECK: cmp w0, w1
|
||||
@ -419,7 +419,7 @@ continue:
|
||||
ret i1 true
|
||||
}
|
||||
|
||||
define i1 @usubo.br.i64(i64 %v1, i64 %v2) {
|
||||
define zeroext i1 @usubo.br.i64(i64 %v1, i64 %v2) {
|
||||
entry:
|
||||
; CHECK-LABEL: usubo.br.i64
|
||||
; CHECK: cmp x0, x1
|
||||
@ -436,12 +436,12 @@ continue:
|
||||
ret i1 true
|
||||
}
|
||||
|
||||
define i1 @smulo.br.i32(i32 %v1, i32 %v2) {
|
||||
define zeroext i1 @smulo.br.i32(i32 %v1, i32 %v2) {
|
||||
entry:
|
||||
; CHECK-LABEL: smulo.br.i32
|
||||
; CHECK: smull x8, w0, w1
|
||||
; CHECK-NEXT: lsr x9, x8, #32
|
||||
; CHECK-NEXT: cmp w9, w8, asr #31
|
||||
; CHECK: smull x[[MREG:[0-9]+]], w0, w1
|
||||
; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x8, #32
|
||||
; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
|
||||
; CHECK-NEXT: b.eq
|
||||
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
|
||||
%val = extractvalue {i32, i1} %t, 0
|
||||
@ -455,12 +455,12 @@ continue:
|
||||
ret i1 true
|
||||
}
|
||||
|
||||
define i1 @smulo.br.i64(i64 %v1, i64 %v2) {
|
||||
define zeroext i1 @smulo.br.i64(i64 %v1, i64 %v2) {
|
||||
entry:
|
||||
; CHECK-LABEL: smulo.br.i64
|
||||
; CHECK: mul x8, x0, x1
|
||||
; CHECK-NEXT: smulh x9, x0, x1
|
||||
; CHECK-NEXT: cmp x9, x8, asr #63
|
||||
; CHECK: mul [[MREG:x[0-9]+]], x0, x1
|
||||
; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
|
||||
; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
|
||||
; CHECK-NEXT: b.eq
|
||||
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
|
||||
%val = extractvalue {i64, i1} %t, 0
|
||||
@ -474,11 +474,11 @@ continue:
|
||||
ret i1 true
|
||||
}
|
||||
|
||||
define i1 @umulo.br.i32(i32 %v1, i32 %v2) {
|
||||
define zeroext i1 @umulo.br.i32(i32 %v1, i32 %v2) {
|
||||
entry:
|
||||
; CHECK-LABEL: umulo.br.i32
|
||||
; CHECK: umull x8, w0, w1
|
||||
; CHECK-NEXT: cmp xzr, x8, lsr #32
|
||||
; CHECK: umull [[MREG:x[0-9]+]], w0, w1
|
||||
; CHECK-NEXT: cmp xzr, [[MREG]], lsr #32
|
||||
; CHECK-NEXT: b.eq
|
||||
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
|
||||
%val = extractvalue {i32, i1} %t, 0
|
||||
@ -492,11 +492,11 @@ continue:
|
||||
ret i1 true
|
||||
}
|
||||
|
||||
define i1 @umulo.br.i64(i64 %v1, i64 %v2) {
|
||||
define zeroext i1 @umulo.br.i64(i64 %v1, i64 %v2) {
|
||||
entry:
|
||||
; CHECK-LABEL: umulo.br.i64
|
||||
; CHECK: umulh x8, x0, x1
|
||||
; CHECK-NEXT: cbz
|
||||
; CHECK: umulh [[REG:x[0-9]+]], x0, x1
|
||||
; CHECK-NEXT: {{cbz|cmp}}
|
||||
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
|
||||
%val = extractvalue {i64, i1} %t, 0
|
||||
%obit = extractvalue {i64, i1} %t, 1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user