From cb9ca905e358698f8732ec94a9aa8059beaa870b Mon Sep 17 00:00:00 2001
From: Bradley Smith <bradley.smith@arm.com>
Date: Wed, 9 Apr 2014 14:44:44 +0000
Subject: [PATCH] [ARM64] Flag setting logical/add/sub immediate instructions
 don't use SP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205895 91177308-0d34-0410-b5e6-96231b3b80d8
---
 .../ARM64/Disassembler/ARM64Disassembler.cpp   | 18 ++++++++++++++----
 test/MC/Disassembler/ARM64/arithmetic.txt      |  4 ++++
 test/MC/Disassembler/ARM64/logical.txt         |  6 ++++++
 3 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp b/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
index 294962c5f35..8f9b79c90a8 100644
--- a/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
+++ b/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
@@ -1417,13 +1417,17 @@ static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
     break;
   case ARM64::ADDXrx64:
-  case ARM64::ADDSXrx64:
   case ARM64::SUBXrx64:
-  case ARM64::SUBSXrx64:
     DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
     break;
+  case ARM64::SUBSXrx64:
+  case ARM64::ADDSXrx64:
+    DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
+    DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
+    DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
+    break;
   }
 
   Inst.addOperand(MCOperand::CreateImm(extend));
@@ -1439,13 +1443,19 @@ static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
   unsigned imm;
 
   if (Datasize) {
-    DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
+    if (Inst.getOpcode() == ARM64::ANDSXri)
+      DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
+    else
+      DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
     DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
     imm = fieldFromInstruction(insn, 10, 13);
     if (!ARM64_AM::isValidDecodeLogicalImmediate(imm, 64))
       return Fail;
   } else {
-    DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
+    if (Inst.getOpcode() == ARM64::ANDSWri)
+      DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
+    else
+      DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
     DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
     imm = fieldFromInstruction(insn, 10, 12);
     if (!ARM64_AM::isValidDecodeLogicalImmediate(imm, 32))
diff --git a/test/MC/Disassembler/ARM64/arithmetic.txt b/test/MC/Disassembler/ARM64/arithmetic.txt
index 2d8fd263b8b..d68f43bd331 100644
--- a/test/MC/Disassembler/ARM64/arithmetic.txt
+++ b/test/MC/Disassembler/ARM64/arithmetic.txt
@@ -49,11 +49,13 @@
 0x83 0x00 0x50 0x31
 0x83 0x00 0x10 0xb1
 0x83 0x00 0x50 0xb1
+0xff 0x83 0x00 0xb1
 
 # CHECK: adds w3, w4, #1024
 # CHECK: adds w3, w4, #4194304
 # CHECK: adds x3, x4, #1024
 # CHECK: adds x3, x4, #4194304
+# CHECK: cmn  sp, #32
 
 0x83 0x00 0x10 0x51
 0x83 0x00 0x50 0x51
@@ -71,11 +73,13 @@
 0x83 0x00 0x50 0x71
 0x83 0x00 0x10 0xf1
 0x83 0x00 0x50 0xf1
+0xff 0x83 0x00 0xf1
 
 # CHECK: subs w3, w4, #1024
 # CHECK: subs w3, w4, #4194304
 # CHECK: subs x3, x4, #1024
 # CHECK: subs x3, x4, #4194304
+# CHECK: cmp  sp, #32
 
 #==---------------------------------------------------------------------------==
 # Add/Subtract register with (optional) shift
diff --git a/test/MC/Disassembler/ARM64/logical.txt b/test/MC/Disassembler/ARM64/logical.txt
index 29db8cbcf41..e3cb3ebe7e0 100644
--- a/test/MC/Disassembler/ARM64/logical.txt
+++ b/test/MC/Disassembler/ARM64/logical.txt
@@ -13,6 +13,7 @@
 0x00 0x00 0x40 0xf2
 0x41 0x0c 0x00 0x72
 0x41 0x0c 0x40 0xf2
+0x5f 0x0c 0x40 0xf2
 
 # CHECK: and  w0, w0, #0x1
 # CHECK: and  x0, x0, #0x1
@@ -23,18 +24,23 @@
 # CHECK: ands x0, x0, #0x1
 # CHECK: ands w1, w2, #0xf
 # CHECK: ands x1, x2, #0xf
+# CHECK: tst x2, #0xf
 
 0x41 0x00 0x12 0x52
 0x41 0x00 0x71 0xd2
+0x5f 0x00 0x71 0xd2
 
 # CHECK: eor w1, w2, #0x4000
 # CHECK: eor x1, x2, #0x8000
+# CHECK: eor sp, x2, #0x8000
 
 0x41 0x00 0x12 0x32
 0x41 0x00 0x71 0xb2
+0x5f 0x00 0x71 0xb2
 
 # CHECK: orr w1, w2, #0x4000
 # CHECK: orr x1, x2, #0x8000
+# CHECK: orr sp, x2, #0x8000
 
 #==---------------------------------------------------------------------------==
 # 5.5.3 Logical (shifted register)