6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-14 11:32:34 +00:00
Code Issues Projects Releases Wiki Activity

Convert DOUT to DEBUG(errs()...).

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79759 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2009-08-22 20:40:21 +00:00
parent fbb594f351
commit cbac788324
1 changed files with 9 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
lib/CodeGen/RegAllocSimple.cpp
View File

@ -23,8 +23,9 @@
#include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Compiler.h" #include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/Statistic.h" #include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
#include <map> #include <map>
@ -196,9 +197,10 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
if (MO.isReg() && MO.getReg() && if (MO.isReg() && MO.getReg() &&
TargetRegisterInfo::isVirtualRegister(MO.getReg())) { TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned virtualReg = (unsigned) MO.getReg(); unsigned virtualReg = (unsigned) MO.getReg();
DOUT << "op: " << MO << "\n"; DEBUG({
DOUT << "\t inst[" << i << "]: "; errs() << "op: " << MO << "\n" << "\t inst[" << i << "]: ";
DEBUG(MI->print(*cerr.stream(), TM)); MI->print(errs(), TM);
});
// make sure the same virtual register maps to the same physical // make sure the same virtual register maps to the same physical
// register in any given instruction // register in any given instruction
@ -226,7 +228,8 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
} }
} }
MO.setReg(physReg); MO.setReg(physReg);
DOUT << "virt: " << virtualReg << ", phys: " << MO.getReg() << "\n"; DEBUG(errs() << "virt: " << virtualReg
<< ", phys: " << MO.getReg() << "\n");
} }
} }
RegClassIdx.clear(); RegClassIdx.clear();
@ -238,7 +241,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
/// runOnMachineFunction - Register allocate the whole function /// runOnMachineFunction - Register allocate the whole function
/// ///
bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) { bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
DOUT << "Machine Function\n"; DEBUG(errs() << "Machine Function\n");
MF = &Fn; MF = &Fn;
TM = &MF->getTarget(); TM = &MF->getTarget();
TRI = TM->getRegisterInfo(); TRI = TM->getRegisterInfo();