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https://github.com/c64scene-ar/llvm-6502.git
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Add AVX2 vpbroadcast support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144967 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem
parent
5a3a9c9371
commit
cbbe33fde4
@ -5115,9 +5115,9 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
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/// 1. A splat BUILD_VECTOR which uses a single scalar load.
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/// 2. A splat shuffle which uses a scalar_to_vector node which comes from
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/// a scalar load.
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/// The scalar load node is returned when a pattern is found,
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/// or SDValue() otherwise.
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static SDValue isVectorBroadcast(SDValue &Op) {
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/// The scalar load node is returned when a pattern is found,
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/// or SDValue() otherwise.
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static SDValue isVectorBroadcast(SDValue &Op, bool hasAVX2) {
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EVT VT = Op.getValueType();
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SDValue V = Op;
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@ -5134,16 +5134,16 @@ static SDValue isVectorBroadcast(SDValue &Op) {
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case ISD::BUILD_VECTOR: {
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// The BUILD_VECTOR node must be a splat.
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if (!isSplatVector(V.getNode()))
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if (!isSplatVector(V.getNode()))
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return SDValue();
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Ld = V.getOperand(0);
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// The suspected load node has several users. Make sure that all
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// The suspected load node has several users. Make sure that all
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// of its users are from the BUILD_VECTOR node.
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if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
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if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
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return SDValue();
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break;
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break;
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}
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case ISD::VECTOR_SHUFFLE: {
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@ -5151,11 +5151,11 @@ static SDValue isVectorBroadcast(SDValue &Op) {
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// Shuffles must have a splat mask where the first element is
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// broadcasted.
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if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
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if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
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return SDValue();
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SDValue Sc = Op.getOperand(0);
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if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
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if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
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return SDValue();
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Ld = Sc.getOperand(0);
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@ -5167,15 +5167,27 @@ static SDValue isVectorBroadcast(SDValue &Op) {
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break;
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}
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}
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// The scalar source must be a normal load.
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if (!ISD::isNormalLoad(Ld.getNode()))
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if (!ISD::isNormalLoad(Ld.getNode()))
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return SDValue();
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bool Is256 = VT.getSizeInBits() == 256;
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bool Is128 = VT.getSizeInBits() == 128;
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unsigned ScalarSize = Ld.getValueType().getSizeInBits();
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if (hasAVX2) {
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// VBroadcast to YMM
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if (Is256 && (ScalarSize == 8 || ScalarSize == 16 ||
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ScalarSize == 32 || ScalarSize == 64 ))
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return Ld;
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// VBroadcast to XMM
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if (Is128 && (ScalarSize == 8 || ScalarSize == 32 ||
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ScalarSize == 16 || ScalarSize == 64 ))
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return Ld;
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}
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// VBroadcast to YMM
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if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
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return Ld;
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@ -5184,6 +5196,7 @@ static SDValue isVectorBroadcast(SDValue &Op) {
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if (Is128 && (ScalarSize == 32))
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return Ld;
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// Unsupported broadcast.
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return SDValue();
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}
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@ -5216,7 +5229,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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return getOnesVector(Op.getValueType(), DAG, dl);
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}
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SDValue LD = isVectorBroadcast(Op);
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SDValue LD = isVectorBroadcast(Op, Subtarget->hasAVX2());
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if (Subtarget->hasAVX() && LD.getNode())
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return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
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@ -6613,7 +6626,7 @@ SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
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return Op;
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// Use vbroadcast whenever the splat comes from a foldable load
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SDValue LD = isVectorBroadcast(Op);
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SDValue LD = isVectorBroadcast(Op, Subtarget->hasAVX2());
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if (Subtarget->hasAVX() && LD.getNode())
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return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
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@ -7189,19 +7189,6 @@ def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
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def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
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(VBROADCASTF128 addr:$src)>;
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def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
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(VBROADCASTSSYrm addr:$src)>;
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def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
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(VBROADCASTSDrm addr:$src)>;
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def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
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(VBROADCASTSSYrm addr:$src)>;
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def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
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(VBROADCASTSDrm addr:$src)>;
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def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
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(VBROADCASTSSrm addr:$src)>;
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def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
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(VBROADCASTSSrm addr:$src)>;
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//===----------------------------------------------------------------------===//
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// VINSERTF128 - Insert packed floating-point values
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@ -7557,6 +7544,40 @@ defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
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int_x86_avx2_pbroadcastq_128,
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int_x86_avx2_pbroadcastq_256>;
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let Predicates = [HasAVX2] in {
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def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
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(VPBROADCASTBrm addr:$src)>;
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def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
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(VPBROADCASTBYrm addr:$src)>;
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def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
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(VPBROADCASTWrm addr:$src)>;
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def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
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(VPBROADCASTWYrm addr:$src)>;
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def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
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(VPBROADCASTDrm addr:$src)>;
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def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
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(VPBROADCASTDYrm addr:$src)>;
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def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
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(VPBROADCASTQrm addr:$src)>;
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def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
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(VPBROADCASTQYrm addr:$src)>;
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}
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// AVX1 broadcast patterns
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def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
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(VBROADCASTSSYrm addr:$src)>;
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def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
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(VBROADCASTSDrm addr:$src)>;
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def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
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(VBROADCASTSSYrm addr:$src)>;
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def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
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(VBROADCASTSDrm addr:$src)>;
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def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
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(VBROADCASTSSrm addr:$src)>;
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def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
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(VBROADCASTSSrm addr:$src)>;
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//===----------------------------------------------------------------------===//
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// VPERM - Permute instructions
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//
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142
test/CodeGen/X86/avx2-vbroadcast.ll
Normal file
142
test/CodeGen/X86/avx2-vbroadcast.ll
Normal file
@ -0,0 +1,142 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
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; CHECK: vpbroadcastb (%
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define <16 x i8> @BB16(i8* %ptr) nounwind uwtable readnone ssp {
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entry:
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%q = load i8* %ptr, align 4
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%q0 = insertelement <16 x i8> undef, i8 %q, i32 0
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%q1 = insertelement <16 x i8> %q0, i8 %q, i32 1
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%q2 = insertelement <16 x i8> %q1, i8 %q, i32 2
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%q3 = insertelement <16 x i8> %q2, i8 %q, i32 3
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%q4 = insertelement <16 x i8> %q3, i8 %q, i32 4
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%q5 = insertelement <16 x i8> %q4, i8 %q, i32 5
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%q6 = insertelement <16 x i8> %q5, i8 %q, i32 6
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%q7 = insertelement <16 x i8> %q6, i8 %q, i32 7
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%q8 = insertelement <16 x i8> %q7, i8 %q, i32 8
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%q9 = insertelement <16 x i8> %q8, i8 %q, i32 9
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%qa = insertelement <16 x i8> %q9, i8 %q, i32 10
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%qb = insertelement <16 x i8> %qa, i8 %q, i32 11
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%qc = insertelement <16 x i8> %qb, i8 %q, i32 12
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%qd = insertelement <16 x i8> %qc, i8 %q, i32 13
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%qe = insertelement <16 x i8> %qd, i8 %q, i32 14
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%qf = insertelement <16 x i8> %qe, i8 %q, i32 15
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ret <16 x i8> %qf
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}
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; CHECK: vpbroadcastb (%
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define <32 x i8> @BB32(i8* %ptr) nounwind uwtable readnone ssp {
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entry:
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%q = load i8* %ptr, align 4
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%q0 = insertelement <32 x i8> undef, i8 %q, i32 0
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%q1 = insertelement <32 x i8> %q0, i8 %q, i32 1
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%q2 = insertelement <32 x i8> %q1, i8 %q, i32 2
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%q3 = insertelement <32 x i8> %q2, i8 %q, i32 3
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%q4 = insertelement <32 x i8> %q3, i8 %q, i32 4
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%q5 = insertelement <32 x i8> %q4, i8 %q, i32 5
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%q6 = insertelement <32 x i8> %q5, i8 %q, i32 6
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%q7 = insertelement <32 x i8> %q6, i8 %q, i32 7
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%q8 = insertelement <32 x i8> %q7, i8 %q, i32 8
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%q9 = insertelement <32 x i8> %q8, i8 %q, i32 9
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%qa = insertelement <32 x i8> %q9, i8 %q, i32 10
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%qb = insertelement <32 x i8> %qa, i8 %q, i32 11
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%qc = insertelement <32 x i8> %qb, i8 %q, i32 12
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%qd = insertelement <32 x i8> %qc, i8 %q, i32 13
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%qe = insertelement <32 x i8> %qd, i8 %q, i32 14
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%qf = insertelement <32 x i8> %qe, i8 %q, i32 15
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%q20 = insertelement <32 x i8> %qf, i8 %q, i32 16
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%q21 = insertelement <32 x i8> %q20, i8 %q, i32 17
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%q22 = insertelement <32 x i8> %q21, i8 %q, i32 18
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%q23 = insertelement <32 x i8> %q22, i8 %q, i32 19
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%q24 = insertelement <32 x i8> %q23, i8 %q, i32 20
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%q25 = insertelement <32 x i8> %q24, i8 %q, i32 21
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%q26 = insertelement <32 x i8> %q25, i8 %q, i32 22
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%q27 = insertelement <32 x i8> %q26, i8 %q, i32 23
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%q28 = insertelement <32 x i8> %q27, i8 %q, i32 24
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%q29 = insertelement <32 x i8> %q28, i8 %q, i32 25
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%q2a = insertelement <32 x i8> %q29, i8 %q, i32 26
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%q2b = insertelement <32 x i8> %q2a, i8 %q, i32 27
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%q2c = insertelement <32 x i8> %q2b, i8 %q, i32 28
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%q2d = insertelement <32 x i8> %q2c, i8 %q, i32 29
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%q2e = insertelement <32 x i8> %q2d, i8 %q, i32 30
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%q2f = insertelement <32 x i8> %q2e, i8 %q, i32 31
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ret <32 x i8> %q2f
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}
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; CHECK: vpbroadcastw (%
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define <8 x i16> @W16(i16* %ptr) nounwind uwtable readnone ssp {
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entry:
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%q = load i16* %ptr, align 4
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%q0 = insertelement <8 x i16> undef, i16 %q, i32 0
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%q1 = insertelement <8 x i16> %q0, i16 %q, i32 1
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%q2 = insertelement <8 x i16> %q1, i16 %q, i32 2
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%q3 = insertelement <8 x i16> %q2, i16 %q, i32 3
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%q4 = insertelement <8 x i16> %q3, i16 %q, i32 4
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%q5 = insertelement <8 x i16> %q4, i16 %q, i32 5
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%q6 = insertelement <8 x i16> %q5, i16 %q, i32 6
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%q7 = insertelement <8 x i16> %q6, i16 %q, i32 7
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ret <8 x i16> %q7
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}
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; CHECK: vpbroadcastw (%
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define <16 x i16> @WW16(i16* %ptr) nounwind uwtable readnone ssp {
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entry:
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%q = load i16* %ptr, align 4
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%q0 = insertelement <16 x i16> undef, i16 %q, i32 0
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%q1 = insertelement <16 x i16> %q0, i16 %q, i32 1
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%q2 = insertelement <16 x i16> %q1, i16 %q, i32 2
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%q3 = insertelement <16 x i16> %q2, i16 %q, i32 3
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%q4 = insertelement <16 x i16> %q3, i16 %q, i32 4
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%q5 = insertelement <16 x i16> %q4, i16 %q, i32 5
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%q6 = insertelement <16 x i16> %q5, i16 %q, i32 6
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%q7 = insertelement <16 x i16> %q6, i16 %q, i32 7
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%q8 = insertelement <16 x i16> %q7, i16 %q, i32 8
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%q9 = insertelement <16 x i16> %q8, i16 %q, i32 9
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%qa = insertelement <16 x i16> %q9, i16 %q, i32 10
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%qb = insertelement <16 x i16> %qa, i16 %q, i32 11
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%qc = insertelement <16 x i16> %qb, i16 %q, i32 12
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%qd = insertelement <16 x i16> %qc, i16 %q, i32 13
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%qe = insertelement <16 x i16> %qd, i16 %q, i32 14
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%qf = insertelement <16 x i16> %qe, i16 %q, i32 15
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ret <16 x i16> %qf
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}
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; CHECK: vpbroadcastd (%
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define <4 x i32> @D32(i32* %ptr) nounwind uwtable readnone ssp {
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entry:
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%q = load i32* %ptr, align 4
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%q0 = insertelement <4 x i32> undef, i32 %q, i32 0
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%q1 = insertelement <4 x i32> %q0, i32 %q, i32 1
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%q2 = insertelement <4 x i32> %q1, i32 %q, i32 2
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%q3 = insertelement <4 x i32> %q2, i32 %q, i32 3
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ret <4 x i32> %q3
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}
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; CHECK: vpbroadcastd (%
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define <8 x i32> @DD32(i32* %ptr) nounwind uwtable readnone ssp {
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entry:
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%q = load i32* %ptr, align 4
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%q0 = insertelement <8 x i32> undef, i32 %q, i32 0
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%q1 = insertelement <8 x i32> %q0, i32 %q, i32 1
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%q2 = insertelement <8 x i32> %q1, i32 %q, i32 2
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%q3 = insertelement <8 x i32> %q2, i32 %q, i32 3
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%q4 = insertelement <8 x i32> %q3, i32 %q, i32 4
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%q5 = insertelement <8 x i32> %q4, i32 %q, i32 5
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%q6 = insertelement <8 x i32> %q5, i32 %q, i32 6
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%q7 = insertelement <8 x i32> %q6, i32 %q, i32 7
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ret <8 x i32> %q7
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}
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; CHECK: vpbroadcastq (%
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define <2 x i64> @Q64(i64* %ptr) nounwind uwtable readnone ssp {
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entry:
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%q = load i64* %ptr, align 4
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%q0 = insertelement <2 x i64> undef, i64 %q, i32 0
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%q1 = insertelement <2 x i64> %q0, i64 %q, i32 1
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ret <2 x i64> %q1
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}
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; CHECK: vpbroadcastq (%
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define <4 x i64> @QQ64(i64* %ptr) nounwind uwtable readnone ssp {
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entry:
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%q = load i64* %ptr, align 4
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%q0 = insertelement <4 x i64> undef, i64 %q, i32 0
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%q1 = insertelement <4 x i64> %q0, i64 %q, i32 1
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%q2 = insertelement <4 x i64> %q1, i64 %q, i32 2
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%q3 = insertelement <4 x i64> %q2, i64 %q, i32 3
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ret <4 x i64> %q3
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}
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