6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-22 10:29:35 +00:00
Code Issues Projects Releases Wiki Activity

Add instruction encoding for DMB/DSB

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91053 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2009-12-10 18:35:32 +00:00
parent 16ced733f3
commit cbd77d2cb1
1 changed files with 11 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/ARM/ARMInstrInfo.td
View File

@ -1574,18 +1574,26 @@ def MOVCCi : AI1<0b1101, (outs GPR:$dst),
//
// memory barriers protect the atomic sequences
let isBarrier = 1 in {
let isBarrier = 1, isPredicable = 0 in {
def Int_MemBarrierV7 : AI<(outs), (ins),
Pseudo, NoItinerary,
"dmb", "",
[(ARMMemBarrier)]>,
Requires<[HasV7]>;
Requires<[HasV7]> {
let Inst{31-4} = 0xf57ff05;
// FIXME: add support for options other than a full system DMB
let Inst{3-0} = 0b1111;
}
def Int_SyncBarrierV7 : AI<(outs), (ins),
Pseudo, NoItinerary,
"dsb", "",
[(ARMSyncBarrier)]>,
Requires<[HasV7]>;
Requires<[HasV7]> {
let Inst{31-4} = 0xf57ff04;
// FIXME: add support for options other than a full system DSB
let Inst{3-0} = 0b1111;
}
}
//===----------------------------------------------------------------------===//