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[RegisterScavenger] Fix handling of predicated instructions
Summary: The RegisterScavenger explicitly ignores <kill> flags on operands of predicated instructions and therefore assumes that such registers remain live. When it then scavenges such a register, it inserts a spill of this (killed) register. This is invalid code and gets flagged up by the verifier. Nowadays kill flags are set correctly on predicated instructions. This patch makes the Scavenger respect them. The bug has so far only been triggered by an internal pass, so I don't have a test case unfortunately. Fixes PR23119. Reviewers: hfinkel, tobiasvk_caf Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9039 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239439 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -103,10 +103,6 @@ void RegScavenger::determineKillsAndDefs() {
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// Find out which registers are early clobbered, killed, defined, and marked
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// def-dead in this instruction.
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// FIXME: The scavenger is not predication aware. If the instruction is
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// predicated, conservatively assume "kill" markers do not actually kill the
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// register. Similarly ignores "dead" markers.
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bool isPred = TII->isPredicated(MI);
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KillRegUnits.reset();
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DefRegUnits.reset();
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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@ -124,7 +120,7 @@ void RegScavenger::determineKillsAndDefs() {
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}
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// Apply the mask.
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(isPred ? DefRegUnits : KillRegUnits) |= TmpRegUnits;
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KillRegUnits |= TmpRegUnits;
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}
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if (!MO.isReg())
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continue;
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@ -136,11 +132,11 @@ void RegScavenger::determineKillsAndDefs() {
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// Ignore undef uses.
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if (MO.isUndef())
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continue;
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if (!isPred && MO.isKill())
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if (MO.isKill())
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addRegUnits(KillRegUnits, Reg);
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} else {
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assert(MO.isDef());
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if (!isPred && MO.isDead())
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if (MO.isDead())
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addRegUnits(KillRegUnits, Reg);
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else
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addRegUnits(DefRegUnits, Reg);
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