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- More mov{h|l}ps patterns.
- Increase cost (complexity) of patterns which match mov{h|l}ps ops. These are preferred over shufps in most cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27835 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -782,12 +782,13 @@ def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
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[(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
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[(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
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let isTwoAddress = 1 in {
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let isTwoAddress = 1 in {
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let AddedCost = 10 in {
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def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
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def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
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"movlps {$src2, $dst|$dst, $src2}",
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"movlps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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[(set VR128:$dst,
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(v4f32 (vector_shuffle VR128:$src1,
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(v4f32 (vector_shuffle VR128:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
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MOVLP_shuffle_mask)))]>;
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MOVLP_shuffle_mask)))]>, Cost<20>;
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def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
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def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
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"movlpd {$src2, $dst|$dst, $src2}",
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"movlpd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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[(set VR128:$dst,
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@ -799,13 +800,14 @@ def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
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[(set VR128:$dst,
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[(set VR128:$dst,
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(v4f32 (vector_shuffle VR128:$src1,
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(v4f32 (vector_shuffle VR128:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
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MOVHP_shuffle_mask)))]>;
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MOVHP_shuffle_mask)))]>, Cost<20>;
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def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
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def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
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"movhpd {$src2, $dst|$dst, $src2}",
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"movhpd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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[(set VR128:$dst,
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(v2f64 (vector_shuffle VR128:$src1,
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(v2f64 (vector_shuffle VR128:$src1,
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(scalar_to_vector (loadf64 addr:$src2)),
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(scalar_to_vector (loadf64 addr:$src2)),
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MOVHP_shuffle_mask)))]>;
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MOVHP_shuffle_mask)))]>;
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} // AddedCost
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}
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}
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def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
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def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
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@ -834,6 +836,7 @@ def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
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addr:$dst)]>;
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addr:$dst)]>;
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let isTwoAddress = 1 in {
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let isTwoAddress = 1 in {
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let AddedCost = 10 in {
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def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"movlhps {$src2, $dst|$dst, $src2}",
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"movlhps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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[(set VR128:$dst,
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@ -845,6 +848,7 @@ def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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[(set VR128:$dst,
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[(set VR128:$dst,
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(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
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(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
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MOVHLPS_shuffle_mask)))]>;
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MOVHLPS_shuffle_mask)))]>;
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} // AddedCost
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}
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}
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def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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@ -2349,6 +2353,22 @@ def : Pat<(v8i16 (X86zexts2vec R16:$src)),
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def : Pat<(v16i8 (X86zexts2vec R8:$src)),
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def : Pat<(v16i8 (X86zexts2vec R8:$src)),
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(MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>;
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(MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>;
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// MOVLP{S|D}rm / MOVHP{S|D}rm.
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let AddedCost = 10 in {
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def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
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MOVLP_shuffle_mask)),
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(MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
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def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
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MOVLP_shuffle_mask)),
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(MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
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def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
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MOVHP_shuffle_mask)),
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(MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
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def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
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MOVHP_shuffle_mask)),
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(MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
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}
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// Splat v2f64 / v2i64
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// Splat v2f64 / v2i64
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def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
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def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
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(v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
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(v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
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@ -2415,6 +2435,9 @@ def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
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def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
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def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
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MOVS_shuffle_mask)),
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MOVS_shuffle_mask)),
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(MOVLPSrr VR128:$src1, VR128:$src2)>;
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(MOVLPSrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
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MOVS_shuffle_mask)),
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(MOVLPDrr VR128:$src1, VR128:$src2)>;
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// 128-bit logical shifts
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// 128-bit logical shifts
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def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
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def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
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