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misched: DAG builder should not track dependencies for SSA defs.
The vast majority of virtual register definitions don't need an entry in the DAG builder's VRegDefs set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151136 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -44,7 +44,7 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
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LoopRegs(MLI, MDT), FirstDbgValue(0) {
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LoopRegs(MLI, MDT), FirstDbgValue(0) {
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assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
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assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
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DbgValues.clear();
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DbgValues.clear();
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assert(!(IsPostRA && MF.getRegInfo().getNumVirtRegs()) &&
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assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
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"Virtual registers must be removed prior to PostRA scheduling");
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"Virtual registers must be removed prior to PostRA scheduling");
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}
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}
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@ -361,6 +361,10 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
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const MachineInstr *MI = SU->getInstr();
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const MachineInstr *MI = SU->getInstr();
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unsigned Reg = MI->getOperand(OperIdx).getReg();
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unsigned Reg = MI->getOperand(OperIdx).getReg();
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// SSA defs do not have output/anti dependencies.
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if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
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return;
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// Add output dependence to the next nearest def of this vreg.
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// Add output dependence to the next nearest def of this vreg.
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//
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//
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// Unless this definition is dead, the output dependence should be
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// Unless this definition is dead, the output dependence should be
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