6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-19 04:29:21 +00:00
Code Issues Projects Releases Wiki Activity

allow R28 to be used for frame calculations without entirely removing it from circulation

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25639 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2006-01-26 03:22:07 +00:00
parent 67caa39e4c
commit cd1544eede
3 changed files with 4 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
lib/Target/Alpha/AlphaInstrFormats.td
View File

@ -45,6 +45,7 @@ class MForm<bits<6> opcode, bit store, bit load, string asmstr, list<dag> patter
let Pattern = pattern;
let isStore = store;
let isLoad = load;
let Defs = [R28]; //We may use this for frame index calculations, so reserve it here
bits<5> Ra;
bits<16> disp;
@ -54,16 +55,7 @@ class MForm<bits<6> opcode, bit store, bit load, string asmstr, list<dag> patter
let Inst{20-16} = Rb;
let Inst{15-0} = disp;
}
class MFormAlt<bits<6> opcode, string asmstr>
: InstAlphaAlt<opcode, asmstr> {
bits<5> Ra;
bits<16> disp;
bits<5> Rb;
let Inst{25-21} = Ra;
let Inst{20-16} = Rb;
let Inst{15-0} = disp;
}
class MfcForm<bits<6> opcode, bits<16> fc, string asmstr>
: InstAlpha<opcode, (ops GPRC:$RA), asmstr> {
bits<5> Ra;
@ -85,15 +77,6 @@ class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr> : InstAlpha<opc
}
//3.3.2
let isBranch = 1, isTerminator = 1 in
class BForm<bits<6> opcode, string asmstr>
: InstAlpha<opcode, (ops GPRC:$RA, s21imm:$DISP), asmstr> {
bits<5> Ra;
bits<21> disp;
let Inst{25-21} = Ra;
let Inst{20-0} = disp;
}
def target : Operand<OtherVT> {}
let isBranch = 1, isTerminator = 1 in
class BFormD<bits<6> opcode, string asmstr, list<dag> pattern>

4
lib/Target/Alpha/AlphaInstrInfo.td
View File

@ -576,8 +576,8 @@ def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i8),
//load address, rellocated gpdist form
let OperandList = (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in {
def LDAg : MFormAlt<0x08, "lda $RA,0($RB)\t\t!gpdisp!$NUM">; //Load address
def LDAHg : MFormAlt<0x09, "ldah $RA,0($RB)\t\t!gpdisp!$NUM">; //Load address
def LDAg : MForm<0x08, 0, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", []>; //Load address
def LDAHg : MForm<0x09, 0, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", []>; //Load address
}
//Load quad, rellocated literal form

2
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -257,7 +257,7 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
" for stack size: " << MF.getFrameInfo()->getStackSize() << "\n");
if (Offset > IMM_HIGH || Offset < IMM_LOW) {
std::cerr << "Unconditionally using R28 for evil purposes\n";
DEBUG(std::cerr << "Unconditionally using R28 for evil purposes Offset: " << Offset << "\n");
//so in this case, we need to use a temporary register, and move the original
//inst off the SP/FP
//fix up the old: