mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-02 07:32:52 +00:00
Avoid inserting a live register more than once.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42410 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
ff37adc0ce
commit
cd1c00cc65
@ -25,6 +25,7 @@
|
|||||||
#include "llvm/Target/TargetInstrInfo.h"
|
#include "llvm/Target/TargetInstrInfo.h"
|
||||||
#include "llvm/Support/Debug.h"
|
#include "llvm/Support/Debug.h"
|
||||||
#include "llvm/Support/Compiler.h"
|
#include "llvm/Support/Compiler.h"
|
||||||
|
#include "llvm/ADT/SmallPtrSet.h"
|
||||||
#include "llvm/ADT/SmallSet.h"
|
#include "llvm/ADT/SmallSet.h"
|
||||||
#include "llvm/ADT/Statistic.h"
|
#include "llvm/ADT/Statistic.h"
|
||||||
#include <climits>
|
#include <climits>
|
||||||
@ -523,17 +524,22 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
|
|||||||
if (LiveRegs.empty())
|
if (LiveRegs.empty())
|
||||||
return false;
|
return false;
|
||||||
|
|
||||||
|
SmallSet<unsigned, 4> RegAdded;
|
||||||
// If this node would clobber any "live" register, then it's not ready.
|
// If this node would clobber any "live" register, then it's not ready.
|
||||||
for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
||||||
I != E; ++I) {
|
I != E; ++I) {
|
||||||
if (I->Cost < 0) {
|
if (I->Cost < 0) {
|
||||||
unsigned Reg = I->Reg;
|
unsigned Reg = I->Reg;
|
||||||
if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep)
|
if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep) {
|
||||||
LRegs.push_back(Reg);
|
if (RegAdded.insert(Reg))
|
||||||
|
LRegs.push_back(Reg);
|
||||||
|
}
|
||||||
for (const unsigned *Alias = MRI->getAliasSet(Reg);
|
for (const unsigned *Alias = MRI->getAliasSet(Reg);
|
||||||
*Alias; ++Alias)
|
*Alias; ++Alias)
|
||||||
if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep)
|
if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) {
|
||||||
LRegs.push_back(*Alias);
|
if (RegAdded.insert(*Alias))
|
||||||
|
LRegs.push_back(*Alias);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -545,12 +551,16 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
|
|||||||
if (!TID.ImplicitDefs)
|
if (!TID.ImplicitDefs)
|
||||||
continue;
|
continue;
|
||||||
for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
|
for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
|
||||||
if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU)
|
if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU) {
|
||||||
LRegs.push_back(*Reg);
|
if (RegAdded.insert(*Reg))
|
||||||
|
LRegs.push_back(*Reg);
|
||||||
|
}
|
||||||
for (const unsigned *Alias = MRI->getAliasSet(*Reg);
|
for (const unsigned *Alias = MRI->getAliasSet(*Reg);
|
||||||
*Alias; ++Alias)
|
*Alias; ++Alias)
|
||||||
if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU)
|
if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) {
|
||||||
LRegs.push_back(*Alias);
|
if (RegAdded.insert(*Alias))
|
||||||
|
LRegs.push_back(*Alias);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
return !LRegs.empty();
|
return !LRegs.empty();
|
||||||
|
Loading…
Reference in New Issue
Block a user