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Mark a static table as const. Shrink opcode size in static tables to uint16_t. Simplify loop iterating over one of those tables. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157367 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -51,9 +51,9 @@ WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
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/// ARM_MLxEntry - Record information about MLA / MLS instructions.
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struct ARM_MLxEntry {
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unsigned MLxOpc; // MLA / MLS opcode
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unsigned MulOpc; // Expanded multiplication opcode
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unsigned AddSubOpc; // Expanded add / sub opcode
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uint16_t MLxOpc; // MLA / MLS opcode
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uint16_t MulOpc; // Expanded multiplication opcode
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uint16_t AddSubOpc; // Expanded add / sub opcode
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bool NegAcc; // True if the acc is negated before the add / sub.
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bool HasLane; // True if instruction has an extra "lane" operand.
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};
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@ -1531,11 +1531,11 @@ ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
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/// This will go away once we can teach tblgen how to set the optional CPSR def
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/// operand itself.
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struct AddSubFlagsOpcodePair {
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unsigned PseudoOpc;
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unsigned MachineOpc;
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uint16_t PseudoOpc;
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uint16_t MachineOpc;
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};
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static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
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static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
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{ARM::ADDSri, ARM::ADDri},
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{ARM::ADDSrr, ARM::ADDrr},
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{ARM::ADDSrsi, ARM::ADDrsi},
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@ -1563,14 +1563,9 @@ static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
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};
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unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
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static const int NPairs =
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sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair);
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for (AddSubFlagsOpcodePair *OpcPair = &AddSubFlagsOpcodeMap[0],
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*End = &AddSubFlagsOpcodeMap[NPairs]; OpcPair != End; ++OpcPair) {
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if (OldOpc == OpcPair->PseudoOpc) {
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return OpcPair->MachineOpc;
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}
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}
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for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
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if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
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return AddSubFlagsOpcodeMap[i].MachineOpc;
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return 0;
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}
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