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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
reimplement the second half of the or/add optimization. We should now
only end up emitting LEA instead of OR. If we aren't able to promote something into an LEA, we should never be emitting it as an ADD. Add some testcases that we emit "or" in cases where we used to produce an "add". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116026 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
0f448b5bf6
commit
cd3167b281
@ -1036,21 +1036,34 @@ def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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"", // orq/addq REG, REG
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[(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
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def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"", // orw/addw REG, imm
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[(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
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def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
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"", // orl/addl REG, imm
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[(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
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def ADD64ri32_DB : I<0, Pseudo,
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(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
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"", // orq/addq REG, imm
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[(set GR64:$dst, (or_is_add GR64:$src1,
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i64immSExt32:$src2))]>;
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def ADD16ri8_DB : I<0, Pseudo,
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(outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
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"", // orw/addw REG, imm8
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[(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
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def ADD32ri8_DB : I<0, Pseudo,
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(outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
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"", // orl/addl REG, imm8
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[(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
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def ADD64ri8_DB : I<0, Pseudo,
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(outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
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"", // orq/addq REG, imm8
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[(set GR64:$dst, (or_is_add GR64:$src1,
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i64immSExt8:$src2))]>;
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}
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def : Pat<(or_is_add GR16:$src1, imm:$src2),
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(ADD16ri GR16:$src1, imm:$src2)>;
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def : Pat<(or_is_add GR32:$src1, imm:$src2),
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(ADD32ri GR32:$src1, imm:$src2)>;
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def : Pat<(or_is_add GR64:$src1, i64immSExt32:$src2),
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(ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
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def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
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(ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
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def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
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(ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
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def : Pat<(or_is_add GR64:$src1, i64immSExt8:$src2),
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(ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
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} // AddedComplexity
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@ -68,14 +68,20 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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{ X86::ADC64rr, X86::ADC64mr },
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{ X86::ADD16ri, X86::ADD16mi },
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{ X86::ADD16ri8, X86::ADD16mi8 },
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{ X86::ADD16ri_DB, X86::ADD16mi | TB_NOT_REVERSABLE },
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{ X86::ADD16ri8_DB, X86::ADD16mi8 | TB_NOT_REVERSABLE },
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{ X86::ADD16rr, X86::ADD16mr },
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{ X86::ADD16rr_DB, X86::ADD16mr | TB_NOT_REVERSABLE },
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{ X86::ADD32ri, X86::ADD32mi },
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{ X86::ADD32ri8, X86::ADD32mi8 },
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{ X86::ADD32ri_DB, X86::ADD32mi | TB_NOT_REVERSABLE },
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{ X86::ADD32ri8_DB, X86::ADD32mi8 | TB_NOT_REVERSABLE },
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{ X86::ADD32rr, X86::ADD32mr },
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{ X86::ADD32rr_DB, X86::ADD32mr | TB_NOT_REVERSABLE },
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{ X86::ADD64ri32, X86::ADD64mi32 },
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{ X86::ADD64ri8, X86::ADD64mi8 },
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{ X86::ADD64ri32_DB,X86::ADD64mi32 | TB_NOT_REVERSABLE },
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{ X86::ADD64ri8_DB, X86::ADD64mi8 | TB_NOT_REVERSABLE },
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{ X86::ADD64rr, X86::ADD64mr },
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{ X86::ADD64rr_DB, X86::ADD64mr | TB_NOT_REVERSABLE },
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{ X86::ADD8ri, X86::ADD8mi },
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@ -1160,6 +1166,8 @@ X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
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break;
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case X86::ADD16ri:
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case X86::ADD16ri8:
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case X86::ADD16ri_DB:
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case X86::ADD16ri8_DB:
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addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
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break;
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case X86::ADD16rr:
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@ -1424,6 +1432,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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}
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case X86::ADD64ri32:
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case X86::ADD64ri8:
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case X86::ADD64ri32_DB:
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case X86::ADD64ri8_DB:
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
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.addReg(Dest, RegState::Define |
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@ -1431,7 +1441,9 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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Src, isKill, MI->getOperand(2).getImm());
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break;
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case X86::ADD32ri:
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case X86::ADD32ri8: {
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case X86::ADD32ri8:
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case X86::ADD32ri_DB:
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case X86::ADD32ri8_DB: {
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
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NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
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@ -1442,6 +1454,8 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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}
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case X86::ADD16ri:
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case X86::ADD16ri8:
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case X86::ADD16ri_DB:
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case X86::ADD16ri8_DB:
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if (DisableLEA16)
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return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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@ -437,9 +437,15 @@ ReSimplify:
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// These are pseudo-ops for OR to help with the OR->ADD transformation. We do
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// this with an ugly goto in case the resultant OR uses EAX and needs the
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// short form.
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case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
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case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
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case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
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case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
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case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
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case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
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case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
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case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
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case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
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case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
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case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
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case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
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// The assembler backend wants to see branches in their small form and relax
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// them to their large form. The JIT can only handle the large form because
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@ -1,9 +1,9 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
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; rdar://7527734
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define i32 @test(i32 %x) nounwind readnone ssp {
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define i32 @test1(i32 %x) nounwind readnone ssp {
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entry:
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; CHECK: test:
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; CHECK: test1:
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; CHECK: leal 3(%rdi), %eax
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%0 = shl i32 %x, 5 ; <i32> [#uses=1]
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%1 = or i32 %0, 3 ; <i32> [#uses=1]
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@ -25,3 +25,37 @@ define i64 @test2(i8 %A, i8 %B) nounwind {
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%H = or i64 %G, %E ; <i64> [#uses=1]
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ret i64 %H
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}
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;; Test that OR is only emitted as LEA, not as ADD.
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define void @test3(i32 %x, i32* %P) nounwind readnone ssp {
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entry:
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; No reason to emit an add here, should be an or.
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; CHECK: test3:
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; CHECK: orl $3, %edi
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%0 = shl i32 %x, 5
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%1 = or i32 %0, 3
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store i32 %1, i32* %P
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ret void
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}
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define i32 @test4(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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%and = and i32 %a, 6
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%and2 = and i32 %b, 16
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%or = or i32 %and2, %and
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ret i32 %or
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; CHECK: test4:
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; CHECK: leal (%rsi,%rdi), %eax
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}
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define void @test5(i32 %a, i32 %b, i32* nocapture %P) nounwind ssp {
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entry:
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%and = and i32 %a, 6
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%and2 = and i32 %b, 16
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%or = or i32 %and2, %and
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store i32 %or, i32* %P, align 4
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ret void
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; CHECK: test5:
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; CHECK: orl
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}
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