From cd700230074b354b63c53da2bdb85a4aa236ee20 Mon Sep 17 00:00:00 2001 From: Elena Demikhovsky Date: Sun, 22 Dec 2013 10:13:18 +0000 Subject: [PATCH] AVX512: SETCC returns i1 for AVX-512 and i8 for all others git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197876 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 13 +++++++++++-- lib/Target/X86/X86InstrAVX512.td | 2 ++ test/CodeGen/X86/avx512-cmp.ll | 13 +++++++++++++ 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index e3f9963a715..cd2f5a2946f 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1313,6 +1313,8 @@ void X86TargetLowering::resetOperationActions() { setOperationAction(ISD::BR_CC, MVT::i1, Expand); setOperationAction(ISD::SETCC, MVT::i1, Custom); setOperationAction(ISD::XOR, MVT::i1, Legal); + setOperationAction(ISD::OR, MVT::i1, Legal); + setOperationAction(ISD::AND, MVT::i1, Legal); setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal); setOperationAction(ISD::LOAD, MVT::v16f32, Legal); setOperationAction(ISD::LOAD, MVT::v8f64, Legal); @@ -10239,8 +10241,9 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG); - return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, - DAG.getConstant(X86CC, MVT::i8), EFLAGS); + MVT SetCCVT = Subtarget->hasAVX512() ? MVT::i1 : MVT::i8; + return DAG.getNode(X86ISD::SETCC, dl, SetCCVT, + DAG.getConstant(X86CC, MVT::i8), EFLAGS); } // isX86LogicalCmp - Return true if opcode is a X86 logical comparison. @@ -17656,6 +17659,12 @@ static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, // FIXME: need symbolic constants for these magic numbers. // See X86ATTInstPrinter.cpp:printSSECC(). unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; + if (Subtarget->hasAVX512()) { + // SETCC type in AVX-512 is MVT::i1 + assert(N->getValueType(0) == MVT::i1 && "Unexpected AND node type"); + return DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00, CMP01, + DAG.getConstant(x86cc, MVT::i8)); + } SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL, CMP00.getValueType(), CMP00, CMP01, DAG.getConstant(x86cc, MVT::i8)); MVT IntVT = (is64BitFP ? MVT::i64 : MVT::i32); diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td index 7bcbc454c9a..d16505fe906 100644 --- a/lib/Target/X86/X86InstrAVX512.td +++ b/lib/Target/X86/X86InstrAVX512.td @@ -911,6 +911,8 @@ let Predicates = [HasAVX512] in { def : Pat<(i1 (X86trunc (i32 GR32:$src))), (COPY_TO_REGCLASS (KMOVWkr $src), VK1)>; + + def : Pat<(i32 (zext VK1:$src)), (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>; } // With AVX-512 only, 8-bit mask is promoted to 16-bit mask. let Predicates = [HasAVX512] in { diff --git a/test/CodeGen/X86/avx512-cmp.ll b/test/CodeGen/X86/avx512-cmp.ll index 5201e32f574..d5ec2e777ce 100644 --- a/test/CodeGen/X86/avx512-cmp.ll +++ b/test/CodeGen/X86/avx512-cmp.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding | FileCheck %s +; CHECK-LABEL: test1 ; CHECK: vucomisd {{.*}}encoding: [0x62 define double @test1(double %a, double %b) nounwind { %tobool = fcmp une double %a, %b @@ -13,6 +14,7 @@ l2: ret double %c1 } +; CHECK-LABEL: test2 ; CHECK: vucomiss {{.*}}encoding: [0x62 define float @test2(float %a, float %b) nounwind { %tobool = fcmp olt float %a, %b @@ -25,3 +27,14 @@ l2: %c1 = fadd float %a, %b ret float %c1 } + +; CHECK-LABEL: test3 +; CHECK: vcmpeqss +; CHECK: kmov +; CHECK: ret +define i32 @test3(float %a, float %b) { + + %cmp10.i = fcmp oeq float %a, %b + %conv11.i = zext i1 %cmp10.i to i32 + ret i32 %conv11.i +}