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[mips] Replace usage of SmallSet with BitVector, which is used to keep track of
defined and used registers. Also add a few helper functions to simplify the code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175224 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
90db35a3e7
commit
cd7319dc5f
@ -15,7 +15,7 @@
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#include "Mips.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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@ -70,14 +70,26 @@ namespace {
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bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
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void insertDefsUses(const MachineInstr &MI, SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses) const;
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/// Initialize RegDefs and RegUses.
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void initRegDefsUses(const MachineInstr &MI, BitVector &RegDefs,
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BitVector &RegUses) const;
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bool isRegInSet(const SmallSet<unsigned, 32> &RegSet, unsigned Reg) const;
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bool isRegInSet(const BitVector &RegSet, unsigned Reg) const;
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bool checkRegDefsUses(const BitVector &RegDefs, const BitVector &RegUses,
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BitVector &NewDefs, BitVector &NewUses,
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unsigned Reg, bool IsDef) const;
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bool checkRegDefsUses(BitVector &RegDefs, BitVector &RegUses,
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const MachineInstr &MI, unsigned Begin,
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unsigned End) const;
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/// This function checks if it is valid to move Candidate to the delay slot
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/// and returns true if it isn't. It also updates load and store flags and
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/// register defs and uses.
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bool delayHasHazard(const MachineInstr &Candidate, bool &SawLoad,
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bool &SawStore, const SmallSet<unsigned, 32> &RegDefs,
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const SmallSet<unsigned, 32> &RegUses) const;
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bool &SawStore, BitVector &RegDefs,
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BitVector &RegUses) const;
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bool findDelayInstr(MachineBasicBlock &MBB, Iter slot, Iter &Filler) const;
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@ -127,10 +139,10 @@ FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) {
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bool Filler::findDelayInstr(MachineBasicBlock &MBB, Iter Slot,
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Iter &Filler) const {
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SmallSet<unsigned, 32> RegDefs;
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SmallSet<unsigned, 32> RegUses;
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unsigned NumRegs = TM.getRegisterInfo()->getNumRegs();
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BitVector RegDefs(NumRegs), RegUses(NumRegs);
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insertDefsUses(*Slot, RegDefs, RegUses);
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initRegDefsUses(*Slot, RegDefs, RegUses);
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bool SawLoad = false;
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bool SawStore = false;
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@ -143,10 +155,8 @@ bool Filler::findDelayInstr(MachineBasicBlock &MBB, Iter Slot,
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if (terminateSearch(*I))
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break;
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if (delayHasHazard(*I, SawLoad, SawStore, RegDefs, RegUses)) {
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insertDefsUses(*I, RegDefs, RegUses);
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if (delayHasHazard(*I, SawLoad, SawStore, RegDefs, RegUses))
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continue;
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}
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Filler = llvm::next(I).base();
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return true;
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@ -155,104 +165,91 @@ bool Filler::findDelayInstr(MachineBasicBlock &MBB, Iter Slot,
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return false;
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}
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bool Filler::checkRegDefsUses(const BitVector &RegDefs,
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const BitVector &RegUses,
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BitVector &NewDefs, BitVector &NewUses,
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unsigned Reg, bool IsDef) const {
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if (IsDef) {
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NewDefs.set(Reg);
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// check whether Reg has already been defined or used.
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return (isRegInSet(RegDefs, Reg) || isRegInSet(RegUses, Reg));
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}
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NewUses.set(Reg);
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// check whether Reg has already been defined.
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return isRegInSet(RegDefs, Reg);
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}
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bool Filler::checkRegDefsUses(BitVector &RegDefs, BitVector &RegUses,
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const MachineInstr &MI, unsigned Begin,
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unsigned End) const {
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unsigned NumRegs = TM.getRegisterInfo()->getNumRegs();
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BitVector NewDefs(NumRegs), NewUses(NumRegs);
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bool HasHazard = false;
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for (unsigned I = Begin; I != End; ++I) {
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const MachineOperand &MO = MI.getOperand(I);
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if (MO.isReg() && MO.getReg())
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HasHazard |= checkRegDefsUses(RegDefs, RegUses, NewDefs, NewUses,
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MO.getReg(), MO.isDef());
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}
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RegDefs |= NewDefs;
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RegUses |= NewUses;
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return HasHazard;
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}
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bool Filler::delayHasHazard(const MachineInstr &Candidate, bool &SawLoad,
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bool &SawStore,
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const SmallSet<unsigned, 32> &RegDefs,
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const SmallSet<unsigned, 32> &RegUses) const {
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if (Candidate.isImplicitDef() || Candidate.isKill())
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return true;
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bool &SawStore, BitVector &RegDefs,
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BitVector &RegUses) const {
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bool HasHazard = (Candidate.isImplicitDef() || Candidate.isKill());
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// Loads or stores cannot be moved past a store to the delay slot
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// and stores cannot be moved past a load.
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if (Candidate.mayLoad()) {
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if (SawStore)
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return true;
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SawLoad = true;
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}
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if (Candidate.mayStore()) {
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if (SawStore)
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return true;
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HasHazard |= SawStore | SawLoad;
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SawStore = true;
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if (SawLoad)
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return true;
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} else if (Candidate.mayLoad()) {
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HasHazard |= SawStore;
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SawLoad = true;
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}
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assert((!Candidate.isCall() && !Candidate.isReturn()) &&
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"Cannot put calls or returns in delay slot.");
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for (unsigned I = 0, E = Candidate.getNumOperands(); I != E; ++I) {
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const MachineOperand &MO = Candidate.getOperand(I);
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unsigned Reg;
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HasHazard |= checkRegDefsUses(RegDefs, RegUses, Candidate, 0,
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Candidate.getNumOperands());
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if (!MO.isReg() || !(Reg = MO.getReg()))
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continue; // skip
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if (MO.isDef()) {
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// check whether Reg is defined or used before delay slot.
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if (isRegInSet(RegDefs, Reg) || isRegInSet(RegUses, Reg))
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return true;
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}
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if (MO.isUse()) {
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// check whether Reg is defined before delay slot.
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if (isRegInSet(RegDefs, Reg))
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return true;
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}
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}
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return false;
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return HasHazard;
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}
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// Helper function for getting a MachineOperand's register number and adding it
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// to RegDefs or RegUses.
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static void insertDefUse(const MachineOperand &MO,
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SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses,
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unsigned ExcludedReg = 0) {
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unsigned Reg;
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if (!MO.isReg() || !(Reg = MO.getReg()) || (Reg == ExcludedReg))
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return;
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if (MO.isDef())
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RegDefs.insert(Reg);
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else if (MO.isUse())
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RegUses.insert(Reg);
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}
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// Insert Defs and Uses of MI into the sets RegDefs and RegUses.
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void Filler::insertDefsUses(const MachineInstr &MI,
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SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses) const {
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unsigned I, E = MI.getDesc().getNumOperands();
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for (I = 0; I != E; ++I)
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insertDefUse(MI.getOperand(I), RegDefs, RegUses);
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void Filler::initRegDefsUses(const MachineInstr &MI, BitVector &RegDefs,
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BitVector &RegUses) const {
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// Add all register operands which are explicit and non-variadic.
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checkRegDefsUses(RegDefs, RegUses, MI, 0, MI.getDesc().getNumOperands());
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// If MI is a call, add RA to RegDefs to prevent users of RA from going into
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// delay slot.
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if (MI.isCall()) {
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RegDefs.insert(Mips::RA);
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return;
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if (MI.isCall())
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RegDefs.set(Mips::RA);
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// Add all implicit register operands of branch instructions except
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// register AT.
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if (MI.isBranch()) {
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checkRegDefsUses(RegDefs, RegUses, MI, MI.getDesc().getNumOperands(),
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MI.getNumOperands());
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RegDefs.reset(Mips::AT);
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}
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// Return if MI is a return.
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if (MI.isReturn())
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return;
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// Examine the implicit operands. Exclude register AT which is in the list of
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// clobbered registers of branch instructions.
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E = MI.getNumOperands();
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for (; I != E; ++I)
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insertDefUse(MI.getOperand(I), RegDefs, RegUses, Mips::AT);
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}
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//returns true if the Reg or its alias is in the RegSet.
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bool Filler::isRegInSet(const SmallSet<unsigned, 32> &RegSet,
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unsigned Reg) const {
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bool Filler::isRegInSet(const BitVector &RegSet, unsigned Reg) const {
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// Check Reg and all aliased Registers.
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for (MCRegAliasIterator AI(Reg, TM.getRegisterInfo(), true);
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AI.isValid(); ++AI)
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if (RegSet.count(*AI))
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if (RegSet.test(*AI))
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return true;
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return false;
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}
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