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[mips] Replace usage of SmallSet with BitVector, which is used to keep track of

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defined and used registers. Also add a few helper functions to simplify the
code. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175224 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-02-14 23:40:57 +00:00
parent 90db35a3e7
commit cd7319dc5f
1 changed files with 83 additions and 86 deletions
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169
lib/Target/Mips/MipsDelaySlotFiller.cpp
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@ -15,7 +15,7 @@
#include "Mips.h" #include "Mips.h"
#include "MipsTargetMachine.h" #include "MipsTargetMachine.h"
#include "llvm/ADT/SmallSet.h" #include "llvm/ADT/BitVector.h"
#include "llvm/ADT/Statistic.h" #include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
@ -70,14 +70,26 @@ namespace {
bool runOnMachineBasicBlock(MachineBasicBlock &MBB); bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
void insertDefsUses(const MachineInstr &MI, SmallSet<unsigned, 32> &RegDefs, /// Initialize RegDefs and RegUses.
SmallSet<unsigned, 32> &RegUses) const; void initRegDefsUses(const MachineInstr &MI, BitVector &RegDefs,
BitVector &RegUses) const;
bool isRegInSet(const SmallSet<unsigned, 32> &RegSet, unsigned Reg) const; bool isRegInSet(const BitVector &RegSet, unsigned Reg) const;
bool checkRegDefsUses(const BitVector &RegDefs, const BitVector &RegUses,
BitVector &NewDefs, BitVector &NewUses,
unsigned Reg, bool IsDef) const;
bool checkRegDefsUses(BitVector &RegDefs, BitVector &RegUses,
const MachineInstr &MI, unsigned Begin,
unsigned End) const;
/// This function checks if it is valid to move Candidate to the delay slot
/// and returns true if it isn't. It also updates load and store flags and
/// register defs and uses.
bool delayHasHazard(const MachineInstr &Candidate, bool &SawLoad, bool delayHasHazard(const MachineInstr &Candidate, bool &SawLoad,
bool &SawStore, const SmallSet<unsigned, 32> &RegDefs, bool &SawStore, BitVector &RegDefs,
const SmallSet<unsigned, 32> &RegUses) const; BitVector &RegUses) const;
bool findDelayInstr(MachineBasicBlock &MBB, Iter slot, Iter &Filler) const; bool findDelayInstr(MachineBasicBlock &MBB, Iter slot, Iter &Filler) const;
@ -127,10 +139,10 @@ FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) {
bool Filler::findDelayInstr(MachineBasicBlock &MBB, Iter Slot, bool Filler::findDelayInstr(MachineBasicBlock &MBB, Iter Slot,
Iter &Filler) const { Iter &Filler) const {
SmallSet<unsigned, 32> RegDefs; unsigned NumRegs = TM.getRegisterInfo()->getNumRegs();
SmallSet<unsigned, 32> RegUses; BitVector RegDefs(NumRegs), RegUses(NumRegs);
insertDefsUses(*Slot, RegDefs, RegUses); initRegDefsUses(*Slot, RegDefs, RegUses);
bool SawLoad = false; bool SawLoad = false;
bool SawStore = false; bool SawStore = false;
@ -143,10 +155,8 @@ bool Filler::findDelayInstr(MachineBasicBlock &MBB, Iter Slot,
if (terminateSearch(*I)) if (terminateSearch(*I))
break; break;
if (delayHasHazard(*I, SawLoad, SawStore, RegDefs, RegUses)) { if (delayHasHazard(*I, SawLoad, SawStore, RegDefs, RegUses))
insertDefsUses(*I, RegDefs, RegUses);
continue; continue;
}
Filler = llvm::next(I).base(); Filler = llvm::next(I).base();
return true; return true;
@ -155,104 +165,91 @@ bool Filler::findDelayInstr(MachineBasicBlock &MBB, Iter Slot,
return false; return false;
} }
bool Filler::checkRegDefsUses(const BitVector &RegDefs,
const BitVector &RegUses,
BitVector &NewDefs, BitVector &NewUses,
unsigned Reg, bool IsDef) const {
if (IsDef) {
NewDefs.set(Reg);
// check whether Reg has already been defined or used.
return (isRegInSet(RegDefs, Reg) || isRegInSet(RegUses, Reg));
}
NewUses.set(Reg);
// check whether Reg has already been defined.
return isRegInSet(RegDefs, Reg);
}
bool Filler::checkRegDefsUses(BitVector &RegDefs, BitVector &RegUses,
const MachineInstr &MI, unsigned Begin,
unsigned End) const {
unsigned NumRegs = TM.getRegisterInfo()->getNumRegs();
BitVector NewDefs(NumRegs), NewUses(NumRegs);
bool HasHazard = false;
for (unsigned I = Begin; I != End; ++I) {
const MachineOperand &MO = MI.getOperand(I);
if (MO.isReg() && MO.getReg())
HasHazard |= checkRegDefsUses(RegDefs, RegUses, NewDefs, NewUses,
MO.getReg(), MO.isDef());
}
RegDefs |= NewDefs;
RegUses |= NewUses;
return HasHazard;
}
bool Filler::delayHasHazard(const MachineInstr &Candidate, bool &SawLoad, bool Filler::delayHasHazard(const MachineInstr &Candidate, bool &SawLoad,
bool &SawStore, bool &SawStore, BitVector &RegDefs,
const SmallSet<unsigned, 32> &RegDefs, BitVector &RegUses) const {
const SmallSet<unsigned, 32> &RegUses) const { bool HasHazard = (Candidate.isImplicitDef() || Candidate.isKill());
if (Candidate.isImplicitDef() || Candidate.isKill())
return true;
// Loads or stores cannot be moved past a store to the delay slot // Loads or stores cannot be moved past a store to the delay slot
// and stores cannot be moved past a load. // and stores cannot be moved past a load.
if (Candidate.mayLoad()) {
if (SawStore)
return true;
SawLoad = true;
}
if (Candidate.mayStore()) { if (Candidate.mayStore()) {
if (SawStore) HasHazard |= SawStore | SawLoad;
return true;
SawStore = true; SawStore = true;
if (SawLoad) } else if (Candidate.mayLoad()) {
return true; HasHazard |= SawStore;
SawLoad = true;
} }
assert((!Candidate.isCall() && !Candidate.isReturn()) && assert((!Candidate.isCall() && !Candidate.isReturn()) &&
"Cannot put calls or returns in delay slot."); "Cannot put calls or returns in delay slot.");
for (unsigned I = 0, E = Candidate.getNumOperands(); I != E; ++I) { HasHazard |= checkRegDefsUses(RegDefs, RegUses, Candidate, 0,
const MachineOperand &MO = Candidate.getOperand(I); Candidate.getNumOperands());
unsigned Reg;
if (!MO.isReg() || !(Reg = MO.getReg())) return HasHazard;
continue; // skip
if (MO.isDef()) {
// check whether Reg is defined or used before delay slot.
if (isRegInSet(RegDefs, Reg) || isRegInSet(RegUses, Reg))
return true;
}
if (MO.isUse()) {
// check whether Reg is defined before delay slot.
if (isRegInSet(RegDefs, Reg))
return true;
}
}
return false;
} }
// Helper function for getting a MachineOperand's register number and adding it void Filler::initRegDefsUses(const MachineInstr &MI, BitVector &RegDefs,
// to RegDefs or RegUses. BitVector &RegUses) const {
static void insertDefUse(const MachineOperand &MO, // Add all register operands which are explicit and non-variadic.
SmallSet<unsigned, 32> &RegDefs, checkRegDefsUses(RegDefs, RegUses, MI, 0, MI.getDesc().getNumOperands());
SmallSet<unsigned, 32> &RegUses,
unsigned ExcludedReg = 0) {
unsigned Reg;
if (!MO.isReg() || !(Reg = MO.getReg()) || (Reg == ExcludedReg))
return;
if (MO.isDef())
RegDefs.insert(Reg);
else if (MO.isUse())
RegUses.insert(Reg);
}
// Insert Defs and Uses of MI into the sets RegDefs and RegUses.
void Filler::insertDefsUses(const MachineInstr &MI,
SmallSet<unsigned, 32> &RegDefs,
SmallSet<unsigned, 32> &RegUses) const {
unsigned I, E = MI.getDesc().getNumOperands();
for (I = 0; I != E; ++I)
insertDefUse(MI.getOperand(I), RegDefs, RegUses);
// If MI is a call, add RA to RegDefs to prevent users of RA from going into // If MI is a call, add RA to RegDefs to prevent users of RA from going into
// delay slot. // delay slot.
if (MI.isCall()) { if (MI.isCall())
RegDefs.insert(Mips::RA); RegDefs.set(Mips::RA);
return;
// Add all implicit register operands of branch instructions except
// register AT.
if (MI.isBranch()) {
checkRegDefsUses(RegDefs, RegUses, MI, MI.getDesc().getNumOperands(),
MI.getNumOperands());
RegDefs.reset(Mips::AT);
} }
// Return if MI is a return.
if (MI.isReturn())
return;
// Examine the implicit operands. Exclude register AT which is in the list of
// clobbered registers of branch instructions.
E = MI.getNumOperands();
for (; I != E; ++I)
insertDefUse(MI.getOperand(I), RegDefs, RegUses, Mips::AT);
} }
//returns true if the Reg or its alias is in the RegSet. //returns true if the Reg or its alias is in the RegSet.
bool Filler::isRegInSet(const SmallSet<unsigned, 32> &RegSet, bool Filler::isRegInSet(const BitVector &RegSet, unsigned Reg) const {
unsigned Reg) const {
// Check Reg and all aliased Registers. // Check Reg and all aliased Registers.
for (MCRegAliasIterator AI(Reg, TM.getRegisterInfo(), true); for (MCRegAliasIterator AI(Reg, TM.getRegisterInfo(), true);
AI.isValid(); ++AI) AI.isValid(); ++AI)
if (RegSet.count(*AI)) if (RegSet.test(*AI))
return true; return true;
return false; return false;
} }