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Add dummy inline asm handling for 'r' constraint. This fixes PR4778
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80085 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -58,6 +58,9 @@ namespace {
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void printCCOperand(const MachineInstr *MI, int OpNum);
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void printInstruction(const MachineInstr *MI); // autogenerated.
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void printMachineInstruction(const MachineInstr * MI);
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant,
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const char *ExtraCode);
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void emitFunctionHeader(const MachineFunction &MF);
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bool runOnMachineFunction(MachineFunction &F);
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@ -243,6 +246,19 @@ void MSP430AsmPrinter::printCCOperand(const MachineInstr *MI, int OpNum) {
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}
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}
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/// PrintAsmOperand - Print out an operand for an inline asm expression.
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///
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bool MSP430AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant,
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const char *ExtraCode) {
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// Does this asm operand have a single letter operand modifier?
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if (ExtraCode && ExtraCode[0])
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return true; // Unknown modifier.
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printOperand(MI, OpNo);
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return false;
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}
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// Force static initialization.
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extern "C" void LLVMInitializeMSP430AsmPrinter() {
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RegisterAsmPrinter<MSP430AsmPrinter> X(TheMSP430Target);
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@ -150,6 +150,44 @@ unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const {
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return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 4;
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}
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//===----------------------------------------------------------------------===//
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// MSP430 Inline Assembly Support
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//===----------------------------------------------------------------------===//
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/// getConstraintType - Given a constraint letter, return the type of
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/// constraint it is for this target.
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TargetLowering::ConstraintType
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MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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case 'r':
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return C_RegisterClass;
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default:
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break;
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}
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}
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return TargetLowering::getConstraintType(Constraint);
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}
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std::pair<unsigned, const TargetRegisterClass*>
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MSP430TargetLowering::
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getRegForInlineAsmConstraint(const std::string &Constraint,
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EVT VT) const {
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if (Constraint.size() == 1) {
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// GCC Constraint Letters
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switch (Constraint[0]) {
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default: break;
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case 'r': // GENERAL_REGS
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if (VT == MVT::i8)
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return std::make_pair(0U, MSP430::GR8RegisterClass);
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return std::make_pair(0U, MSP430::GR16RegisterClass);
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}
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}
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return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
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}
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//===----------------------------------------------------------------------===//
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// Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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@ -84,6 +84,11 @@ namespace llvm {
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG);
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TargetLowering::ConstraintType
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getConstraintType(const std::string &Constraint) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
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MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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16
test/CodeGen/MSP430/inline-asm.ll
Normal file
16
test/CodeGen/MSP430/inline-asm.ll
Normal file
@ -0,0 +1,16 @@
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; RUN: llvm-as < %s | llc
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; PR4778
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target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
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target triple = "msp430-generic-generic"
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define signext i8 @__nesc_atomic_start() nounwind {
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entry:
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%0 = tail call i16 asm sideeffect "mov r2, $0", "=r"() nounwind ; <i16> [#uses=1]
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%1 = trunc i16 %0 to i8 ; <i8> [#uses=1]
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%and3 = lshr i8 %1, 3 ; <i8> [#uses=1]
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%conv1 = and i8 %and3, 1 ; <i8> [#uses=1]
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tail call void asm sideeffect "dint", ""() nounwind
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tail call void asm sideeffect "nop", ""() nounwind
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tail call void asm sideeffect "", "~{memory}"() nounwind
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ret i8 %conv1
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}
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