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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-02 07:11:49 +00:00
Optimize some special cases for SSE4a insertqi
Summary: Since the upper 64 bits of the destination register are undefined when performing this operation, we can substitute it and let the optimizer figure out that only a copy is needed. Also added range merging, if an instruction copies a range that can be merged with a previous copied range. Added test cases for both optimizations. Reviewers: grosbach, nadav CC: llvm-commits Differential Revision: http://reviews.llvm.org/D3357 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207055 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Filipe Cabecinhas
parent
8bd9405026
commit
cd9f6b870e
@ -578,6 +578,73 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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break;
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}
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case Intrinsic::x86_sse4a_insertqi: {
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// insertqi x, y, 64, 0 can just copy y's lower bits and leave the top
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// ones undef
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// TODO: eventually we should lower this intrinsic to IR
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if (auto CIWidth = dyn_cast<ConstantInt>(II->getArgOperand(2))) {
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if (auto CIStart = dyn_cast<ConstantInt>(II->getArgOperand(3))) {
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if (CIWidth->equalsInt(64) && CIStart->isZero()) {
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Value *Vec = II->getArgOperand(1);
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Value *Undef = UndefValue::get(Vec->getType());
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const uint32_t Mask[] = { 0, 2 };
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return ReplaceInstUsesWith(
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CI,
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Builder->CreateShuffleVector(
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Vec, Undef, ConstantDataVector::get(
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II->getContext(), ArrayRef<uint32_t>(Mask))));
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} else if (auto Source =
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dyn_cast<IntrinsicInst>(II->getArgOperand(0))) {
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if (Source->hasOneUse() &&
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Source->getArgOperand(1) == II->getArgOperand(1)) {
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// If the source of the insert has only one use and it's another
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// insert (and they're both inserting from the same vector), try to
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// bundle both together.
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auto CISourceWidth =
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dyn_cast<ConstantInt>(Source->getArgOperand(2));
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auto CISourceStart =
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dyn_cast<ConstantInt>(Source->getArgOperand(3));
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if (CISourceStart && CISourceWidth) {
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unsigned Start = CIStart->getZExtValue();
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unsigned Width = CIWidth->getZExtValue();
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unsigned End = Start + Width;
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unsigned SourceStart = CISourceStart->getZExtValue();
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unsigned SourceWidth = CISourceWidth->getZExtValue();
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unsigned SourceEnd = SourceStart + SourceWidth;
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unsigned NewStart, NewWidth;
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bool ShouldReplace = false;
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if (Start <= SourceStart && SourceStart <= End) {
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NewStart = Start;
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NewWidth = std::max(End, SourceEnd) - NewStart;
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ShouldReplace = true;
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} else if (SourceStart <= Start && Start <= SourceEnd) {
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NewStart = SourceStart;
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NewWidth = std::max(SourceEnd, End) - NewStart;
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ShouldReplace = true;
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}
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if (ShouldReplace) {
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Constant *ConstantWidth = ConstantInt::get(
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II->getArgOperand(2)->getType(), NewWidth, false);
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Constant *ConstantStart = ConstantInt::get(
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II->getArgOperand(3)->getType(), NewStart, false);
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Value *Args[4] = { Source->getArgOperand(0),
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II->getArgOperand(1), ConstantWidth,
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ConstantStart };
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Module *M = CI.getParent()->getParent()->getParent();
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Value *F =
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Intrinsic::getDeclaration(M, Intrinsic::x86_sse4a_insertqi);
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return ReplaceInstUsesWith(CI, Builder->CreateCall(F, Args));
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}
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}
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}
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}
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}
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}
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break;
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}
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case Intrinsic::x86_avx_vpermilvar_ps:
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case Intrinsic::x86_avx_vpermilvar_ps_256:
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case Intrinsic::x86_avx_vpermilvar_pd:
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@ -209,6 +209,103 @@ define <4 x float> @test_select(float %f, float %g) {
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ret <4 x float> %ret
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}
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; We should optimize these two redundant insertqi into one
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; CHECK: define <2 x i64> @testInsertTwice(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertTwice(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 32)
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; CHECK-NOT: insertqi
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 32)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 32)
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ret <2 x i64> %2
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}
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; The result of this insert is the second arg, since the top 64 bits of
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; the result are undefined, and we copy the bottom 64 bits from the
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; second arg
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; CHECK: define <2 x i64> @testInsert64Bits(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsert64Bits(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: ret <2 x i64> %i
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 64, i8 0)
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ret <2 x i64> %1
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}
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; Test the several types of ranges and ordering that exist for two insertqi
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; CHECK: define <2 x i64> @testInsertContainedRange(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertContainedRange(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0)
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; CHECK: ret <2 x i64> %[[RES]]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 16)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertContainedRange_2(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertContainedRange_2(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0)
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; CHECK: ret <2 x i64> %[[RES]]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 16)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 0)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertOverlappingRange(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertOverlappingRange(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 48, i8 0)
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; CHECK: ret <2 x i64> %[[RES]]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 16)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertOverlappingRange_2(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertOverlappingRange_2(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 48, i8 0)
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; CHECK: ret <2 x i64> %[[RES]]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 16)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 0)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertAdjacentRange(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertAdjacentRange(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 48, i8 0)
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; CHECK: ret <2 x i64> %[[RES]]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertAdjacentRange_2(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertAdjacentRange_2(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 48, i8 0)
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; CHECK: ret <2 x i64> %[[RES]]
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 32)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 0)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertDisjointRange(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertDisjointRange(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 0)
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; CHECK: tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32)
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 0)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32)
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ret <2 x i64> %2
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}
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; CHECK: define <2 x i64> @testInsertDisjointRange_2(<2 x i64> %v, <2 x i64> %i)
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define <2 x i64> @testInsertDisjointRange_2(<2 x i64> %v, <2 x i64> %i) {
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; CHECK: tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 0)
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; CHECK: tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32)
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%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 0)
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%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32)
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ret <2 x i64> %2
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}
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; CHECK: declare <2 x i64> @llvm.x86.sse4a.insertqi
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declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind
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declare <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float>, <4 x i32>)
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define <4 x float> @test_vpermilvar_ps(<4 x float> %v) {
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; CHECK-LABEL: @test_vpermilvar_ps(
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