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Enabling 3DNow! prefetch instruction for a few AMD processors: bobcat, jaguar,
bulldozer and piledriver. Support for the instruction itself seems to have already been added in r178040. Differential Revision: http://llvm-reviews.chandlerc.com/D1933 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192828 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -292,19 +292,19 @@ def : Proc<"amdfam10", [FeatureSSE4A,
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FeaturePOPCNT, FeatureSlowBTMem]>;
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// Bobcat
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def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
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FeatureLZCNT, FeaturePOPCNT]>;
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FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT]>;
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// Jaguar
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def : Proc<"btver2", [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
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FeatureAES, FeaturePCLMUL, FeatureBMI,
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FeatureF16C, FeatureMOVBE, FeatureLZCNT,
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FeaturePOPCNT]>;
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FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
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FeatureBMI, FeatureF16C, FeatureMOVBE,
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FeatureLZCNT, FeaturePOPCNT]>;
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// Bulldozer
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def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
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FeatureAES, FeaturePCLMUL,
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FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
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FeatureLZCNT, FeaturePOPCNT]>;
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// Piledriver
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def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
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FeatureAES, FeaturePCLMUL,
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FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
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FeatureF16C, FeatureLZCNT,
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FeaturePOPCNT, FeatureBMI, FeatureTBM,
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FeatureFMA]>;
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@ -687,7 +687,7 @@ def HasADX : Predicate<"Subtarget->hasADX()">;
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def HasSHA : Predicate<"Subtarget->hasSHA()">;
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def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
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def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
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def HasPrefetchW : Predicate<"Subtarget->has3DNow() || Subtarget->hasPRFCHW()">;
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def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
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def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
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def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
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def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
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@ -2,6 +2,8 @@
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; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s
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; RUN: llc < %s -march=x86 -mattr=+sse -mattr=+prfchw | FileCheck %s -check-prefix=PRFCHW
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; RUN: llc < %s -march=x86 -mcpu=slm | FileCheck %s -check-prefix=SLM
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; RUN: llc < %s -march=x86 -mcpu=btver2 | FileCheck %s -check-prefix=PRFCHW
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; RUN: llc < %s -march=x86 -mcpu=btver2 -mattr=-prfchw | FileCheck %s -check-prefix=NOPRFCHW
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; rdar://10538297
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@ -12,6 +14,7 @@ entry:
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; CHECK: prefetcht0
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; CHECK: prefetchnta
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; PRFCHW: prefetchw
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; NOPRFCHW-NOT: prefetchw
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; SLM: prefetchw
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2, i32 1 )
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