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Long double patch 8 of N: make it partially work in
SSE mode (all but conversions <-> other FP types, I think): >>Do not mark all-80-bit operations as "Requires[FPStack]" (which really means "not SSE"). >>Refactor load-and-extend to facilitate this. >>Update comments. >>Handle long double in SSE when computing FP_REG_KILL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40906 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen
parent
31cac2e04a
commit
cdbe4d3ebe
@ -424,7 +424,10 @@ static const TableEntry OpcodeTable[] = {
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{ X86::LD_Fp164 , X86::LD_F1 },
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{ X86::LD_Fp180 , X86::LD_F1 },
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{ X86::LD_Fp32m , X86::LD_F32m },
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{ X86::LD_Fp32m64 , X86::LD_F32m },
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{ X86::LD_Fp32m80 , X86::LD_F32m },
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{ X86::LD_Fp64m , X86::LD_F64m },
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{ X86::LD_Fp64m80 , X86::LD_F64m },
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{ X86::LD_Fp80m , X86::LD_F80m },
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{ X86::MUL_Fp32m , X86::MUL_F32m },
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{ X86::MUL_Fp64m , X86::MUL_F64m },
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@ -479,61 +479,61 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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// If we are emitting FP stack code, scan the basic block to determine if this
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// block defines any FP values. If so, put an FP_REG_KILL instruction before
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// the terminator of the block.
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if (!Subtarget->hasSSE2()) {
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// Note that FP stack instructions *are* used in SSE code when returning
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// values, but these are not live out of the basic block, so we don't need
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// an FP_REG_KILL in this case either.
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bool ContainsFPCode = false;
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// Scan all of the machine instructions in these MBBs, checking for FP
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// stores.
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MachineFunction::iterator MBBI = FirstMBB;
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do {
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for (MachineBasicBlock::iterator I = MBBI->begin(), E = MBBI->end();
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!ContainsFPCode && I != E; ++I) {
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if (I->getNumOperands() != 0 && I->getOperand(0).isRegister()) {
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const TargetRegisterClass *clas;
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for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
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if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() &&
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MRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
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((clas = RegMap->getRegClass(I->getOperand(0).getReg())) ==
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X86::RFP32RegisterClass ||
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clas == X86::RFP64RegisterClass ||
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clas == X86::RFP80RegisterClass)) {
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ContainsFPCode = true;
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break;
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}
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}
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}
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}
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} while (!ContainsFPCode && &*(MBBI++) != BB);
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// Check PHI nodes in successor blocks. These PHI's will be lowered to have
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// a copy of the input value in this block.
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if (!ContainsFPCode) {
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// Final check, check LLVM BB's that are successors to the LLVM BB
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// corresponding to BB for FP PHI nodes.
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const BasicBlock *LLVMBB = BB->getBasicBlock();
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const PHINode *PN;
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for (succ_const_iterator SI = succ_begin(LLVMBB), E = succ_end(LLVMBB);
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!ContainsFPCode && SI != E; ++SI) {
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for (BasicBlock::const_iterator II = SI->begin();
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(PN = dyn_cast<PHINode>(II)); ++II) {
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if (PN->getType()->isFloatingPoint()) {
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// Note that FP stack instructions *are* used in SSE code for long double,
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// so we do need this check.
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bool ContainsFPCode = false;
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// Scan all of the machine instructions in these MBBs, checking for FP
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// stores. (RFP32 and RFP64 will not exist in SSE mode, but RFP80 might.)
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MachineFunction::iterator MBBI = FirstMBB;
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do {
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for (MachineBasicBlock::iterator I = MBBI->begin(), E = MBBI->end();
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!ContainsFPCode && I != E; ++I) {
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if (I->getNumOperands() != 0 && I->getOperand(0).isRegister()) {
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const TargetRegisterClass *clas;
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for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
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if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() &&
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MRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
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((clas = RegMap->getRegClass(I->getOperand(0).getReg())) ==
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X86::RFP32RegisterClass ||
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clas == X86::RFP64RegisterClass ||
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clas == X86::RFP80RegisterClass)) {
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ContainsFPCode = true;
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break;
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}
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}
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}
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}
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} while (!ContainsFPCode && &*(MBBI++) != BB);
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// Finally, if we found any FP code, emit the FP_REG_KILL instruction.
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if (ContainsFPCode) {
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BuildMI(*BB, BB->getFirstTerminator(),
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TM.getInstrInfo()->get(X86::FP_REG_KILL));
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++NumFPKill;
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// Check PHI nodes in successor blocks. These PHI's will be lowered to have
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// a copy of the input value in this block. In SSE mode, we only care about
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// 80-bit values.
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if (!ContainsFPCode) {
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// Final check, check LLVM BB's that are successors to the LLVM BB
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// corresponding to BB for FP PHI nodes.
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const BasicBlock *LLVMBB = BB->getBasicBlock();
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const PHINode *PN;
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for (succ_const_iterator SI = succ_begin(LLVMBB), E = succ_end(LLVMBB);
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!ContainsFPCode && SI != E; ++SI) {
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for (BasicBlock::const_iterator II = SI->begin();
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(PN = dyn_cast<PHINode>(II)); ++II) {
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if (PN->getType()==Type::X86_FP80Ty ||
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(!Subtarget->hasSSE2() && PN->getType()->isFloatingPoint())) {
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ContainsFPCode = true;
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break;
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}
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}
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}
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}
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// Finally, if we found any FP code, emit the FP_REG_KILL instruction.
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if (ContainsFPCode) {
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BuildMI(*BB, BB->getFirstTerminator(),
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TM.getInstrInfo()->get(X86::FP_REG_KILL));
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++NumFPKill;
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}
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}
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/// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
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@ -2,7 +2,7 @@
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the Evan Cheng and is distributed under
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// This file was developed by Evan Cheng and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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@ -48,10 +48,6 @@ def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
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def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
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[SDNPHasChain]>;
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def extloadf80f32 : PatFrag<(ops node:$ptr), (f80 (extloadf32 node:$ptr))>;
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def extloadf80f64 : PatFrag<(ops node:$ptr), (f80 (extloadf64 node:$ptr))>;
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def extloadf64f32 : PatFrag<(ops node:$ptr), (f64 (extloadf32 node:$ptr))>;
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//===----------------------------------------------------------------------===//
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// FPStack pattern fragments
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//===----------------------------------------------------------------------===//
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@ -116,18 +112,18 @@ let isTerminator = 1 in
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let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
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def FP_REG_KILL : I<0, Pseudo, (outs), (ins), "#FP_REG_KILL", []>;
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// All FP Stack operations are represented with three instructions here. The
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// first two instructions, generated by the instruction selector, uses "RFP32"
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// or "RFP64" registers: traditional register files to reference 32-bit or
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// 64-bit floating point values. These sizes apply to the values, not the
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// registers, which are always 64 bits; RFP32 and RFP64 can be copied to
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// each other without losing information. These instructions are all psuedo
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// instructions and use the "_Fp" suffix.
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// In some cases there are additional variants with a mixture of 32-bit and
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// 64-bit registers.
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// All FP Stack operations are represented with four instructions here. The
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// first three instructions, generated by the instruction selector, use "RFP32"
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// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit,
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// 64-bit or 80-bit floating point values. These sizes apply to the values,
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// not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be
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// copied to each other without losing information. These instructions are all
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// pseudo instructions and use the "_Fp" suffix.
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// In some cases there are additional variants with a mixture of different
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// register sizes.
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// The second instruction is defined with FPI, which is the actual instruction
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// emitted by the assembler. These use "RST" registers, although frequently
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// the actual register(s) used are implicit. These are always 64-bits.
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// the actual register(s) used are implicit. These are always 80 bits.
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// The FP stackifier pass converts one to the other after register allocation
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// occurs.
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//
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@ -135,7 +131,7 @@ let isTerminator = 1 in
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// a pattern) and the FPI instruction should have emission info (e.g. opcode
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// encoding and asm printing info).
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// Random Pseudo Instructions.
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// Pseudo Instructions for FP stack return values.
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def FpGETRESULT32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP,
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[(set RFP32:$dst, X86fpget)]>; // FPR = ST(0)
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@ -155,6 +151,8 @@ def FpSETRESULT80 : FpI_<(outs), (ins RFP80:$src), SpecialFP,
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[(X86fpset RFP80:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
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// FpI - Floating Point Psuedo Instruction template. Predicated on FPStack.
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// Note that f80-only instructions are used even in SSE mode and use FpI_
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// not this predicate.
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class FpI<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
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FpI_<outs, ins, fp, pattern>, Requires<[FPStack]>;
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@ -167,7 +165,7 @@ def MOV_Fp8032 : FpI<(outs RFP32:$dst), (ins RFP80:$src), SpecialFP, []>;
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def MOV_Fp3280 : FpI<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []>;
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def MOV_Fp8064 : FpI<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>;
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def MOV_Fp6480 : FpI<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>;
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def MOV_Fp8080 : FpI<(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>;
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def MOV_Fp8080 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>;
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// Factoring for arithmetic.
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multiclass FPBinary_rr<SDNode OpNode> {
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@ -177,7 +175,7 @@ def _Fp32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP,
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[(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
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def _Fp64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP,
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[(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
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def _Fp80 : FpI<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP,
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def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP,
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[(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
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}
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// The FopST0 series are not included here because of the irregularities
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@ -193,13 +191,13 @@ def _Fp64m : FpI<(outs RFP64:$dst), (ins RFP64:$src1, f64mem:$src2), OneArgFPRW
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(OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
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def _Fp64m32: FpI<(outs RFP64:$dst), (ins RFP64:$src1, f32mem:$src2), OneArgFPRW,
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[(set RFP64:$dst,
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(OpNode RFP64:$src1, (extloadf64f32 addr:$src2)))]>;
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def _Fp80m32: FpI<(outs RFP80:$dst), (ins RFP80:$src1, f32mem:$src2), OneArgFPRW,
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(OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>;
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def _Fp80m32: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f32mem:$src2), OneArgFPRW,
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[(set RFP80:$dst,
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(OpNode RFP80:$src1, (extloadf80f32 addr:$src2)))]>;
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def _Fp80m64: FpI<(outs RFP80:$dst), (ins RFP80:$src1, f64mem:$src2), OneArgFPRW,
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(OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>;
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def _Fp80m64: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f64mem:$src2), OneArgFPRW,
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[(set RFP80:$dst,
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(OpNode RFP80:$src1, (extloadf80f64 addr:$src2)))]>;
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(OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>;
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def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),
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!strconcat("f", !strconcat(asmstring, "{s}\t$src"))>;
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def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),
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@ -217,10 +215,10 @@ def _FpI16m64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), OneArgFP
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def _FpI32m64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), OneArgFPRW,
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[(set RFP64:$dst, (OpNode RFP64:$src1,
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(X86fild addr:$src2, i32)))]>;
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def _FpI16m80 : FpI<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), OneArgFPRW,
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def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), OneArgFPRW,
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[(set RFP80:$dst, (OpNode RFP80:$src1,
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(X86fild addr:$src2, i16)))]>;
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def _FpI32m80 : FpI<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), OneArgFPRW,
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def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), OneArgFPRW,
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[(set RFP80:$dst, (OpNode RFP80:$src1,
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(X86fild addr:$src2, i32)))]>;
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def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),
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@ -275,7 +273,7 @@ def _Fp32 : FpI<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,
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[(set RFP32:$dst, (OpNode RFP32:$src))]>;
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def _Fp64 : FpI<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW,
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[(set RFP64:$dst, (OpNode RFP64:$src))]>;
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def _Fp80 : FpI<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
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def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
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[(set RFP80:$dst, (OpNode RFP80:$src))]>;
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def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9;
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}
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@ -290,7 +288,7 @@ def TST_Fp32 : FpI<(outs), (ins RFP32:$src), OneArgFP,
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[]>;
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def TST_Fp64 : FpI<(outs), (ins RFP64:$src), OneArgFP,
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[]>;
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def TST_Fp80 : FpI<(outs), (ins RFP80:$src), OneArgFP,
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def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP,
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[]>;
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def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
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@ -302,7 +300,7 @@ multiclass FPCMov<PatLeaf cc> {
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def _Fp64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), CondMovFP,
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[(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
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cc))]>;
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def _Fp80 : FpI<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), CondMovFP,
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def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), CondMovFP,
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[(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
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cc))]>;
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}
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@ -340,8 +338,14 @@ def LD_Fp32m : FpI<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
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[(set RFP32:$dst, (loadf32 addr:$src))]>;
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def LD_Fp64m : FpI<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP,
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[(set RFP64:$dst, (loadf64 addr:$src))]>;
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def LD_Fp80m : FpI<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP,
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def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP,
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[(set RFP80:$dst, (loadf80 addr:$src))]>;
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def LD_Fp32m64 : FpI<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP,
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[(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>;
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def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP,
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[(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>;
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def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP,
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[(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>;
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def ILD_Fp16m32: FpI<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP,
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[(set RFP32:$dst, (X86fild addr:$src, i16))]>;
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def ILD_Fp32m32: FpI<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP,
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@ -354,11 +358,11 @@ def ILD_Fp32m64: FpI<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP,
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[(set RFP64:$dst, (X86fild addr:$src, i32))]>;
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def ILD_Fp64m64: FpI<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP,
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[(set RFP64:$dst, (X86fild addr:$src, i64))]>;
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def ILD_Fp16m80: FpI<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP,
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def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP,
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[(set RFP80:$dst, (X86fild addr:$src, i16))]>;
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def ILD_Fp32m80: FpI<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,
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def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,
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[(set RFP80:$dst, (X86fild addr:$src, i32))]>;
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def ILD_Fp64m80: FpI<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
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def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
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[(set RFP80:$dst, (X86fild addr:$src, i64))]>;
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def ST_Fp32m : FpI<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP,
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@ -367,9 +371,9 @@ def ST_Fp64m32 : FpI<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP,
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[(truncstoref32 RFP64:$src, addr:$op)]>;
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def ST_Fp64m : FpI<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP,
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[(store RFP64:$src, addr:$op)]>;
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def ST_Fp80m32 : FpI<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP,
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def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP,
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[(truncstoref32 RFP80:$src, addr:$op)]>;
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def ST_Fp80m64 : FpI<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP,
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def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP,
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[(truncstoref64 RFP80:$src, addr:$op)]>;
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// FST does not support 80-bit memory target; FSTP must be used.
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@ -378,7 +382,7 @@ def ST_FpP64m32 : FpI<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
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def ST_FpP64m : FpI<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
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def ST_FpP80m32 : FpI<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>;
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||||
def ST_FpP80m64 : FpI<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>;
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def ST_FpP80m : FpI<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
|
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def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
|
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[(store RFP80:$src, addr:$op)]>;
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def IST_Fp16m32 : FpI<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
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||||
def IST_Fp32m32 : FpI<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
|
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@ -386,9 +390,9 @@ def IST_Fp64m32 : FpI<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>;
|
||||
def IST_Fp16m64 : FpI<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>;
|
||||
def IST_Fp32m64 : FpI<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>;
|
||||
def IST_Fp64m64 : FpI<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>;
|
||||
def IST_Fp16m80 : FpI<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>;
|
||||
def IST_Fp32m80 : FpI<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>;
|
||||
def IST_Fp64m80 : FpI<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
|
||||
def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>;
|
||||
def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>;
|
||||
def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
|
||||
|
||||
def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
|
||||
def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
|
||||
@ -456,9 +460,9 @@ def LD_Fp064 : FpI<(outs RFP64:$dst), (ins), ZeroArgFP,
|
||||
[(set RFP64:$dst, fpimm0)]>;
|
||||
def LD_Fp164 : FpI<(outs RFP64:$dst), (ins), ZeroArgFP,
|
||||
[(set RFP64:$dst, fpimm1)]>;
|
||||
def LD_Fp080 : FpI<(outs RFP80:$dst), (ins), ZeroArgFP,
|
||||
def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
|
||||
[(set RFP80:$dst, fpimm0)]>;
|
||||
def LD_Fp180 : FpI<(outs RFP80:$dst), (ins), ZeroArgFP,
|
||||
def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
|
||||
[(set RFP80:$dst, fpimm1)]>;
|
||||
}
|
||||
|
||||
@ -475,9 +479,9 @@ def UCOM_Fpr64 : FpI<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
|
||||
[]>; // FPSW = cmp ST(0) with ST(i)
|
||||
def UCOM_FpIr64: FpI<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
|
||||
[(X86cmp RFP64:$lhs, RFP64:$rhs)]>; // CC = ST(0) cmp ST(i)
|
||||
def UCOM_Fpr80 : FpI<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
|
||||
def UCOM_Fpr80 : FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
|
||||
[]>; // FPSW = cmp ST(0) with ST(i)
|
||||
def UCOM_FpIr80: FpI<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
|
||||
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
|
||||
[(X86cmp RFP80:$lhs, RFP80:$rhs)]>; // CC = ST(0) cmp ST(i)
|
||||
|
||||
def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
|
||||
@ -510,12 +514,12 @@ def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
|
||||
// Non-Instruction Patterns
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Required for RET of f32 / f64 values.
|
||||
// Required for RET of f32 / f64 / f80 values.
|
||||
def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>;
|
||||
def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>;
|
||||
def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>;
|
||||
|
||||
// Required for CALL which return f32 / f64 values.
|
||||
// Required for CALL which return f32 / f64 / f80 values.
|
||||
def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>;
|
||||
def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, RFP64:$src)>;
|
||||
def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>;
|
||||
@ -528,19 +532,12 @@ def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStack]>;
|
||||
def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStack]>;
|
||||
def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStack]>;
|
||||
def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStack]>;
|
||||
def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>, Requires<[FPStack]>;
|
||||
def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>, Requires<[FPStack]>;
|
||||
def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>;
|
||||
def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>;
|
||||
|
||||
// Used to conv. i64 to f64 since there isn't a SSE version.
|
||||
def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>;
|
||||
|
||||
def : Pat<(extloadf80f32 addr:$src),
|
||||
(MOV_Fp3280 (LD_Fp32m addr:$src))>, Requires<[FPStack]>;
|
||||
def : Pat<(extloadf80f64 addr:$src),
|
||||
(MOV_Fp6480 (LD_Fp64m addr:$src))>, Requires<[FPStack]>;
|
||||
def : Pat<(extloadf64f32 addr:$src),
|
||||
(MOV_Fp3264 (LD_Fp32m addr:$src))>, Requires<[FPStack]>;
|
||||
|
||||
def : Pat<(f64 (fextend RFP32:$src)), (MOV_Fp3264 RFP32:$src)>, Requires<[FPStack]>;
|
||||
def : Pat<(f80 (fextend RFP32:$src)), (MOV_Fp3280 RFP32:$src)>, Requires<[FPStack]>;
|
||||
def : Pat<(f80 (fextend RFP64:$src)), (MOV_Fp6480 RFP64:$src)>, Requires<[FPStack]>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user