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[mips] Refactor shift instructions with register operands. Separate encoding

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170650 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-12-20 03:48:24 +00:00
parent 0dad34a9bf
commit cdc0c59d1e
3 changed files with 28 additions and 15 deletions
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8
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -110,9 +110,9 @@ def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>;
def DSLL : shift_rotate_imm64<"dsll", shl>, SRA_FM<0x38, 0>;
def DSRL : shift_rotate_imm64<"dsrl", srl>, SRA_FM<0x3a, 0>;
def DSRA : shift_rotate_imm64<"dsra", sra>, SRA_FM<0x3b, 0>;
def DSLLV : shift_rotate_reg<0x14, 0x00, "dsllv", shl, CPU64Regs>;
def DSRLV : shift_rotate_reg<0x16, 0x00, "dsrlv", srl, CPU64Regs>;
def DSRAV : shift_rotate_reg<0x17, 0x00, "dsrav", sra, CPU64Regs>;
def DSLLV : shift_rotate_reg<"dsllv", shl, CPU64Regs>, SRLV_FM<0x14, 0>;
def DSRLV : shift_rotate_reg<"dsrlv", srl, CPU64Regs>, SRLV_FM<0x16, 0>;
def DSRAV : shift_rotate_reg<"dsrav", sra, CPU64Regs>, SRLV_FM<0x17, 0>;
def DSLL32 : shift_rotate_imm64<"dsll32">, SRA_FM<0x3c, 0>;
def DSRL32 : shift_rotate_imm64<"dsrl32">, SRA_FM<0x3e, 0>;
def DSRA32 : shift_rotate_imm64<"dsra32">, SRA_FM<0x3f, 0>;
@ -121,7 +121,7 @@ def DSRA32 : shift_rotate_imm64<"dsra32">, SRA_FM<0x3f, 0>;
let Predicates = [HasMips64r2, HasStdEnc],
DecoderNamespace = "Mips64" in {
def DROTR : shift_rotate_imm64<"drotr", rotr>, SRA_FM<0x3a, 1>;
def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>;
def DROTRV : shift_rotate_reg<"drotrv", rotr, CPU64Regs>, SRLV_FM<0x16, 1>;
}
let DecoderNamespace = "Mips64" in {

16
lib/Target/Mips/MipsInstrFormats.td
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@ -236,6 +236,22 @@ class SRA_FM<bits<6> funct, bit rotate> {
let Inst{5-0} = funct;
}
class SRLV_FM<bits<6> funct, bit rotate> {
bits<5> rd;
bits<5> rt;
bits<5> rs;
bits<32> Inst;
let Inst{31-26} = 0;
let Inst{25-21} = rs;
let Inst{20-16} = rt;
let Inst{15-11} = rd;
let Inst{10-7} = 0;
let Inst{6} = rotate;
let Inst{5-0} = funct;
}
//===----------------------------------------------------------------------===//
//
// FLOATING POINT INSTRUCTION FORMATS

19
lib/Target/Mips/MipsInstrInfo.td
View File

@ -394,13 +394,10 @@ class shift_rotate_imm<string opstr, PatFrag PF, Operand ImmOpnd,
class shift_rotate_imm32<string opstr, SDPatternOperator OpNode = null_frag> :
shift_rotate_imm<opstr, immZExt5, shamt, CPURegs, OpNode>;
class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
SDNode OpNode, RegisterClass RC>:
FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
!strconcat(instr_asm, "\t$rd, $rt, $rs"),
[(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> {
let shamt = isRotate;
}
class shift_rotate_reg<string opstr, SDNode OpNode, RegisterClass RC>:
InstSE<(outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
!strconcat(opstr, "\t$rd, $rt, $rs"),
[(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu, FrmR>;
// Load Upper Imediate
class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
@ -939,14 +936,14 @@ def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
def SLL : shift_rotate_imm32<"sll", shl>, SRA_FM<0, 0>;
def SRL : shift_rotate_imm32<"srl", srl>, SRA_FM<2, 0>;
def SRA : shift_rotate_imm32<"sra", sra>, SRA_FM<3, 0>;
def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>;
def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>;
def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>;
def SLLV : shift_rotate_reg<"sllv", shl, CPURegs>, SRLV_FM<4, 0>;
def SRLV : shift_rotate_reg<"srlv", srl, CPURegs>, SRLV_FM<6, 0>;
def SRAV : shift_rotate_reg<"srav", sra, CPURegs>, SRLV_FM<7, 0>;
// Rotate Instructions
let Predicates = [HasMips32r2, HasStdEnc] in {
def ROTR : shift_rotate_imm32<"rotr", rotr>, SRA_FM<2, 1>;
def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>;
def ROTRV : shift_rotate_reg<"rotrv", rotr, CPURegs>, SRLV_FM<6, 1>;
}
/// Load and Store Instructions