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Assembly parsing for 3-register variant of VLD1.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-10-21 20:02:19 +00:00
parent a48aab924d
commit cdcfa28056
8 changed files with 46 additions and 23 deletions
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12
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@@ -920,6 +920,11 @@ public:
return VectorList.Count == 2;
}
bool isVecListThreeD() const {
if (Kind != k_VectorList) return false;
return VectorList.Count == 3;
}
bool isVectorIndex8() const {
if (Kind != k_VectorIndex) return false;
return VectorIndex.Val < 8;
@@ -1519,6 +1524,13 @@ public:
Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
}
void addVecListThreeDOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
// Only the first register actually goes on the instruction. The rest
// are implied by the opcode.
Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
}
void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));