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[InstCombine/PowerPC] Fix single-precision QPX load/store replacement
The QPX single-precision load/store intrinsics have implied truncation/extension from/to the declared value type of <4 x double> to the memory type of <4 x float>. When we can prove the alignment of the pointer argument, and thus replace the intrinsic with a regular load or store, we need to load or store the correct data type (<4 x float>) instead of (<4 x double>). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236973 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -624,9 +624,12 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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// Turn PPC QPX qvlfs -> load if the pointer is known aligned.
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if (getOrEnforceKnownAlignment(II->getArgOperand(0), 16, DL, II, AC, DT) >=
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16) {
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Type *VTy = VectorType::get(Builder->getFloatTy(),
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II->getType()->getVectorNumElements());
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Value *Ptr = Builder->CreateBitCast(II->getArgOperand(0),
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PointerType::getUnqual(II->getType()));
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return new LoadInst(Ptr);
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PointerType::getUnqual(VTy));
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Value *Load = Builder->CreateLoad(Ptr);
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return new FPExtInst(Load, II->getType());
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}
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break;
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case Intrinsic::ppc_qpx_qvlfd:
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@ -642,10 +645,12 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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// Turn PPC QPX qvstfs -> store if the pointer is known aligned.
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if (getOrEnforceKnownAlignment(II->getArgOperand(1), 16, DL, II, AC, DT) >=
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16) {
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Type *OpPtrTy =
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PointerType::getUnqual(II->getArgOperand(0)->getType());
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Type *VTy = VectorType::get(Builder->getFloatTy(),
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II->getArgOperand(0)->getType()->getVectorNumElements());
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Value *TOp = Builder->CreateFPTrunc(II->getArgOperand(0), VTy);
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Type *OpPtrTy = PointerType::getUnqual(VTy);
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Value *Ptr = Builder->CreateBitCast(II->getArgOperand(1), OpPtrTy);
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return new StoreInst(II->getArgOperand(0), Ptr);
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return new StoreInst(TOp, Ptr);
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}
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break;
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case Intrinsic::ppc_qpx_qvstfd:
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@ -28,6 +28,7 @@ entry:
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; CHECK-LABEL: @test1a
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; CHECK-NOT: @llvm.ppc.qpx.qvlfs
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; CHECK-NOT: load <4 x double>
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; CHECK: ret <4 x double>
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%v0 = load <4 x float>, <4 x float>* %h, align 8
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@ -62,7 +63,9 @@ entry:
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ret <4 x float> %v0
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; CHECK-LABEL: @test2
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; CHECK: fptrunc <4 x double> %d to <4 x float>
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; CHECK-NOT: @llvm.ppc.qpx.qvstfs
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; CHECK-NOT: store <4 x double>
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; CHECK: ret <4 x float>
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}
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