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Add support for the isLoad and isStore flags, needed by the instruction scheduler

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16554 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
2004-09-28 21:01:45 +00:00
parent 5b71d3af35
commit cdd66b524f
3 changed files with 6 additions and 0 deletions
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2
utils/TableGen/CodeGenTarget.cpp
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@@ -195,6 +195,8 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
isBranch = R->getValueAsBit("isBranch");
isBarrier = R->getValueAsBit("isBarrier");
isCall = R->getValueAsBit("isCall");
isLoad = R->getValueAsBit("isLoad");
isStore = R->getValueAsBit("isStore");
isTwoAddress = R->getValueAsBit("isTwoAddress");
isTerminator = R->getValueAsBit("isTerminator");
hasDelaySlot = R->getValueAsBit("hasDelaySlot");