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add the "eq" condition code

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implement a movcond instruction


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29857 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2006-08-24 17:19:08 +00:00
parent 6f602de3b6
commit cdda88cd12
3 changed files with 13 additions and 8 deletions
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4
lib/Target/ARM/ARM.h
View File

@ -23,7 +23,8 @@ namespace llvm {
// Enums corresponding to ARM condition codes
namespace ARMCC {
enum CondCodes {
NE
NE,
EQ
};
}
@ -31,6 +32,7 @@ namespace llvm {
switch (CC) {
default: assert(0 && "Unknown condition code");
case ARMCC::NE: return "ne";
case ARMCC::EQ: return "eq";
}
}

6
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -84,6 +84,7 @@ static ARMCC::CondCodes DAGCCToARMCC(ISD::CondCode CC) {
switch (CC) {
default: assert(0 && "Unknown condition code!");
case ISD::SETNE: return ARMCC::NE;
case ISD::SETEQ: return ARMCC::EQ;
}
}
@ -317,11 +318,10 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
SDOperand TrueVal = Op.getOperand(2);
SDOperand FalseVal = Op.getOperand(3);
assert(CC == ISD::SETEQ);
SDOperand ARMCC = DAG.getConstant(DAGCCToARMCC(CC), MVT::i32);
SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
return DAG.getNode(ARMISD::SELECT, MVT::i32, FalseVal, TrueVal, Cmp);
return DAG.getNode(ARMISD::SELECT, MVT::i32, FalseVal, TrueVal, ARMCC, Cmp);
}
static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {

11
lib/Target/ARM/ARMInstrInfo.td
View File

@ -54,7 +54,10 @@ def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
[SDNPHasChain, SDNPOptInFlag]>;
def armselect : SDNode<"ARMISD::SELECT", SDTIntBinOp, [SDNPInFlag, SDNPOutFlag]>;
def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>;
def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>;
def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
@ -111,9 +114,9 @@ def andrr : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
[(set IntRegs:$dst, (and IntRegs:$a, IntRegs:$b))]>;
let isTwoAddress = 1 in {
def moveq : InstARM<(ops IntRegs:$dst, IntRegs:$false, IntRegs:$true),
"moveq $dst, $true",
[(set IntRegs:$dst, (armselect IntRegs:$true, IntRegs:$false))]>;
def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false, IntRegs:$true, CCOp:$cc),
"mov$cc $dst, $true",
[(set IntRegs:$dst, (armselect IntRegs:$true, IntRegs:$false, imm:$cc))]>;
}
def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),