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bah, must generate all results
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24574 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1191,8 +1191,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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break;
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case ISD::READCYCLECOUNTER:
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
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if (Tmp1 != Node->getOperand(0))
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Result = DAG.getNode(ISD::READCYCLECOUNTER, MVT::i64, Tmp1);
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if (Tmp1 != Node->getOperand(0)) {
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std::vector<MVT::ValueType> rtypes;
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std::vector<SDOperand> rvals;
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rtypes.push_back(MVT::i64);
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rtypes.push_back(MVT::Other);
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rvals.push_back(Tmp1);
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Result = DAG.getNode(ISD::READCYCLECOUNTER, rtypes, rvals);
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}
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// Since rdcc produce two values, make sure to remember that we legalized
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// both of them.
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