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https://github.com/c64scene-ar/llvm-6502.git
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Annotate the rest of X86InstrInfo.td with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178048 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
af4c7300b9
commit
cdf7625960
@ -760,7 +760,7 @@ def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
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//
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// Nop
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let neverHasSideEffects = 1 in {
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let neverHasSideEffects = 1, SchedRW = [WriteZero] in {
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def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
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def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
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"nop{w}\t$zero", [], IIC_NOP>, TB, OpSize;
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@ -771,8 +771,9 @@ let neverHasSideEffects = 1 in {
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// Constructing a stack frame.
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def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
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"enter\t$len, $lvl", [], IIC_ENTER>;
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"enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
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let SchedRW = [WriteALU] in {
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let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
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def LEAVE : I<0xC9, RawFrm,
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(outs), (ins), "leave", [], IIC_LEAVE>,
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@ -782,6 +783,7 @@ let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
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def LEAVE64 : I<0xC9, RawFrm,
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(outs), (ins), "leave", [], IIC_LEAVE>,
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Requires<[In64BitMode]>;
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} // SchedRW
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//===----------------------------------------------------------------------===//
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// Miscellaneous Instructions.
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@ -868,10 +870,10 @@ def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
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let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
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def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
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Requires<[In64BitMode]>;
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Requires<[In64BitMode]>, Sched<[WriteLoad]>;
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let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
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def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
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Requires<[In64BitMode]>;
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Requires<[In64BitMode]>, Sched<[WriteStore]>;
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let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
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mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
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@ -901,53 +903,56 @@ let Defs = [EFLAGS] in {
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def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
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"bsf{w}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
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IIC_BSF>, TB, OpSize;
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IIC_BSF>, TB, OpSize, Sched<[WriteShift]>;
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def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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"bsf{w}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
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IIC_BSF>, TB, OpSize;
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IIC_BSF>, TB, OpSize, Sched<[WriteShiftLd]>;
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def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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"bsf{l}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], IIC_BSF>, TB;
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[(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], IIC_BSF>, TB,
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Sched<[WriteShift]>;
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def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
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"bsf{l}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
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IIC_BSF>, TB;
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IIC_BSF>, TB, Sched<[WriteShiftLd]>;
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def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"bsf{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
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IIC_BSF>, TB;
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IIC_BSF>, TB, Sched<[WriteShift]>;
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def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"bsf{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
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IIC_BSF>, TB;
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IIC_BSF>, TB, Sched<[WriteShiftLd]>;
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def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
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"bsr{w}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))], IIC_BSR>,
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TB, OpSize;
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TB, OpSize, Sched<[WriteShift]>;
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def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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"bsr{w}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
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IIC_BSR>, TB,
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OpSize;
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OpSize, Sched<[WriteShiftLd]>;
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def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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"bsr{l}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], IIC_BSR>, TB;
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[(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], IIC_BSR>, TB,
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Sched<[WriteShift]>;
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def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
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"bsr{l}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
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IIC_BSR>, TB;
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IIC_BSR>, TB, Sched<[WriteShiftLd]>;
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def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"bsr{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BSR>, TB;
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[(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BSR>, TB,
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Sched<[WriteShift]>;
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def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"bsr{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
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IIC_BSR>, TB;
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IIC_BSR>, TB, Sched<[WriteShiftLd]>;
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} // Defs = [EFLAGS]
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let SchedRW = [WriteMicrocoded] in {
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// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
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let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
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def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", [], IIC_MOVS>;
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@ -975,7 +980,7 @@ def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", [], IIC_CMPS>;
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def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", [], IIC_CMPS>, OpSize;
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def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>;
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def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", [], IIC_CMPS>;
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} // SchedRW
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//===----------------------------------------------------------------------===//
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// Move Instructions.
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@ -1226,7 +1231,7 @@ def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
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"btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
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} // SchedRW
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let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd] in {
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let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
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def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
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"btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
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OpSize, TB;
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@ -1266,7 +1271,7 @@ def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
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"btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
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} // SchedRW
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let mayLoad = 1, mayStore = 1 in {
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let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
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def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
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"btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
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OpSize, TB;
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@ -1347,7 +1352,7 @@ def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
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// operand is referenced, the atomicity is ensured.
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multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
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InstrItinClass itin> {
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let Constraints = "$val = $dst" in {
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let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
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def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
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(ins GR8:$val, i8mem:$ptr),
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!strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
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@ -1382,6 +1387,7 @@ multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
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defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
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// Swap between registers.
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let SchedRW = [WriteALU] in {
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let Constraints = "$val = $dst" in {
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def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
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"xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
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@ -1406,9 +1412,9 @@ def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
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Requires<[In64BitMode]>;
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def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
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"xchg{q}\t{$src, %rax|RAX, $src}", [], IIC_XCHG_REG>;
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} // SchedRW
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let SchedRW = [WriteALU] in {
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def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
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"xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
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def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
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@ -1418,8 +1424,9 @@ def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
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"xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
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def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
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"xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
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} // SchedRW
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let mayLoad = 1, mayStore = 1 in {
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let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
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def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
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"xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
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def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
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@ -1432,6 +1439,7 @@ def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
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}
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let SchedRW = [WriteALU] in {
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def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
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"cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
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IIC_CMPXCHG_REG8>, TB;
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@ -1444,7 +1452,9 @@ def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
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def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
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"cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
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IIC_CMPXCHG_REG>, TB;
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} // SchedRW
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let SchedRW = [WriteALULd, WriteRMW] in {
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let mayLoad = 1, mayStore = 1 in {
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def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
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"cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
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@ -1468,7 +1478,7 @@ let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
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def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
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"cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
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TB, Requires<[HasCmpxchg16b]>;
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} // SchedRW
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// Lock instruction prefix
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@ -1491,17 +1501,21 @@ def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
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// String manipulation instructions
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let SchedRW = [WriteMicrocoded] in {
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def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", [], IIC_LODS>;
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def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", [], IIC_LODS>, OpSize;
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def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>;
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def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", [], IIC_LODS>;
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}
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let SchedRW = [WriteSystem] in {
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def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", [], IIC_OUTS>;
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def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", [], IIC_OUTS>, OpSize;
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def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>;
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}
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// Flag instructions
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let SchedRW = [WriteALU] in {
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def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
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def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
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def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
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@ -1511,9 +1525,11 @@ def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
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def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
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def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
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}
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// Table lookup instructions
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def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>;
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def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
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Sched<[WriteLoad]>;
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let SchedRW = [WriteMicrocoded] in {
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// ASCII Adjust After Addition
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