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Use movss to insert_vector_elt(v, s, 0).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27782 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3015,28 +3015,41 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32);
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return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
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} else if (MVT::getSizeInBits(BaseVT) == 32) {
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// Use two pinsrw instructions to insert a 32 bit value.
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unsigned Idx = cast<ConstantSDNode>(N2)->getValue();
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Idx <<= 1;
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if (MVT::isFloatingPoint(N1.getValueType())) {
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if (N1.getOpcode() == ISD::LOAD) {
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// Just load directly from f32mem to R32.
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N1 = DAG.getLoad(MVT::i32, N1.getOperand(0), N1.getOperand(1),
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N1.getOperand(2));
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} else {
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N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
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N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
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N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
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DAG.getConstant(0, MVT::i32));
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if (Idx == 0) {
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// Use a movss.
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N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1);
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MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
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MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
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std::vector<SDOperand> MaskVec;
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MaskVec.push_back(DAG.getConstant(4, BaseVT));
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for (unsigned i = 1; i <= 3; ++i)
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MaskVec.push_back(DAG.getConstant(i, BaseVT));
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1,
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DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec));
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} else {
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// Use two pinsrw instructions to insert a 32 bit value.
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Idx <<= 1;
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if (MVT::isFloatingPoint(N1.getValueType())) {
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if (N1.getOpcode() == ISD::LOAD) {
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// Just load directly from f32mem to R32.
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N1 = DAG.getLoad(MVT::i32, N1.getOperand(0), N1.getOperand(1),
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N1.getOperand(2));
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} else {
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N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
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N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
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N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
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DAG.getConstant(0, MVT::i32));
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}
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}
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N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
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N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
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DAG.getConstant(Idx, MVT::i32));
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N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8));
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N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
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DAG.getConstant(Idx+1, MVT::i32));
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return DAG.getNode(ISD::BIT_CONVERT, VT, N0);
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}
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N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
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N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
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DAG.getConstant(Idx, MVT::i32));
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N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8));
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N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
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DAG.getConstant(Idx+1, MVT::i32));
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return DAG.getNode(ISD::BIT_CONVERT, VT, N0);
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}
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return SDOperand();
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@ -2414,6 +2414,11 @@ def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
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MOVSLDUP_shuffle_mask)),
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(MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
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// vector_shuffle v1, v2 <4, 1, 2, 3>
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def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
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MOVS_shuffle_mask)),
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(MOVLPSrr VR128:$src1, VR128:$src2)>;
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// 128-bit logical shifts
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def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
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(v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
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