mirror of
https://github.com/c64scene-ar/llvm-6502.git
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ARM: fix thumb literal loads decoding
This fixes two previous issues: - Negative offsets were not correctly disassembled - The decoded opcodes were not the right one git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184180 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Amaury de la Vieuville
parent
cea0032f73
commit
ce046b98ed
@ -959,6 +959,8 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
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let Inst{19-16} = addr{16-13}; // Rn
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let Inst{15-12} = Rt;
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let Inst{11-0} = addr{11-0}; // imm
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let DecoderMethod = "DecodeT2LoadImm12";
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}
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def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
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opc, "\t$Rt, $addr",
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@ -979,6 +981,8 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
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let Inst{9} = addr{8}; // U
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let Inst{8} = 0; // The W bit.
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let Inst{7-0} = addr{7-0}; // imm
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let DecoderMethod = "DecodeT2LoadImm8";
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}
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def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
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opc, ".w\t$Rt, $addr",
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@ -1019,6 +1023,8 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
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bits<12> addr;
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let Inst{15-12} = Rt{3-0};
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let Inst{11-0} = addr{11-0};
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let DecoderMethod = "DecodeT2LoadLabel";
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}
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}
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@ -1228,15 +1234,15 @@ defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
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// Loads with zero extension
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defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
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rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
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GPR, UnOpFrag<(zextloadi16 node:$Src)>>;
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defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
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rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
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GPR, UnOpFrag<(zextloadi8 node:$Src)>>;
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// Loads with sign extension
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defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
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rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
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GPR, UnOpFrag<(sextloadi16 node:$Src)>>;
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defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
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rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
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GPR, UnOpFrag<(sextloadi8 node:$Src)>>;
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
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// Load doubleword
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@ -1373,6 +1379,8 @@ class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
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let Inst{11} = 1;
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let Inst{10-8} = 0b110; // PUW.
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let Inst{7-0} = addr{7-0};
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let DecoderMethod = "DecodeT2LoadT";
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}
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def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
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@ -347,6 +347,14 @@ static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void* Decoder);
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static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void* Decoder);
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static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void* Decoder);
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static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void* Decoder);
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static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
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@ -3188,19 +3196,9 @@ static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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DecodeStatus S = MCDisassembler::Success;
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switch (Inst.getOpcode()) {
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case ARM::t2PLDs:
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case ARM::t2PLDWs:
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case ARM::t2PLIs:
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break;
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default: {
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unsigned Rt = fieldFromInstruction(Insn, 12, 4);
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if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
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return MCDisassembler::Fail;
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}
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}
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unsigned Rt = fieldFromInstruction(Insn, 12, 4);
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unsigned Rn = fieldFromInstruction(Insn, 16, 4);
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if (Rn == 0xF) {
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switch (Inst.getOpcode()) {
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case ARM::t2LDRBs:
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@ -3215,19 +3213,32 @@ static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
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case ARM::t2LDRSBs:
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Inst.setOpcode(ARM::t2LDRSBpci);
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break;
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case ARM::t2PLDs:
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case ARM::t2LDRs:
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Inst.setOpcode(ARM::t2LDRpci);
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break;
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case ARM::t2PLDs: {
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Inst.setOpcode(ARM::t2PLDi12);
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Inst.addOperand(MCOperand::CreateReg(ARM::PC));
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break;
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int imm = fieldFromInstruction(Insn, 0, 12);
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if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1;
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Inst.addOperand(MCOperand::CreateImm(imm));
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return S;
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}
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default:
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return MCDisassembler::Fail;
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}
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int imm = fieldFromInstruction(Insn, 0, 12);
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if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1;
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Inst.addOperand(MCOperand::CreateImm(imm));
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return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
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}
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return S;
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switch (Inst.getOpcode()) {
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case ARM::t2PLDs:
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case ARM::t2PLDWs:
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case ARM::t2PLIs:
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break;
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default:
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if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
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return MCDisassembler::Fail;
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}
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unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
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@ -3239,6 +3250,154 @@ static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
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return S;
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}
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static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void* Decoder) {
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DecodeStatus S = MCDisassembler::Success;
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unsigned Rn = fieldFromInstruction(Insn, 16, 4);
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unsigned Rt = fieldFromInstruction(Insn, 12, 4);
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unsigned U = fieldFromInstruction(Insn, 9, 1);
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unsigned imm = fieldFromInstruction(Insn, 0, 8);
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imm |= (U << 8);
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imm |= (Rn << 9);
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if (Rn == 15) {
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switch (Inst.getOpcode()) {
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case ARM::t2LDRi8:
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Inst.setOpcode(ARM::t2LDRpci);
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break;
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case ARM::t2LDRBi8:
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Inst.setOpcode(ARM::t2LDRBpci);
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break;
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case ARM::t2LDRSBi8:
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Inst.setOpcode(ARM::t2LDRSBpci);
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break;
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case ARM::t2LDRHi8:
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Inst.setOpcode(ARM::t2LDRHpci);
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break;
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case ARM::t2LDRSHi8:
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Inst.setOpcode(ARM::t2LDRSHpci);
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break;
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default:
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return MCDisassembler::Fail;
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}
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return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
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}
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if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
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return MCDisassembler::Fail;
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if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
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return MCDisassembler::Fail;
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return S;
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}
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static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void* Decoder) {
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DecodeStatus S = MCDisassembler::Success;
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unsigned Rn = fieldFromInstruction(Insn, 16, 4);
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unsigned Rt = fieldFromInstruction(Insn, 12, 4);
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unsigned imm = fieldFromInstruction(Insn, 0, 12);
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imm |= (Rn << 13);
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if (Rn == 15) {
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switch (Inst.getOpcode()) {
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case ARM::t2LDRi12:
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Inst.setOpcode(ARM::t2LDRpci);
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break;
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case ARM::t2LDRHi12:
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Inst.setOpcode(ARM::t2LDRHpci);
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break;
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case ARM::t2LDRSHi12:
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Inst.setOpcode(ARM::t2LDRSHpci);
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break;
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case ARM::t2LDRBi12:
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Inst.setOpcode(ARM::t2LDRBpci);
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break;
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case ARM::t2LDRSBi12:
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Inst.setOpcode(ARM::t2LDRSBpci);
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break;
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default:
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return MCDisassembler::Fail;
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}
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return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
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}
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if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
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return MCDisassembler::Fail;
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if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
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return MCDisassembler::Fail;
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return S;
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}
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static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void* Decoder) {
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DecodeStatus S = MCDisassembler::Success;
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unsigned Rn = fieldFromInstruction(Insn, 16, 4);
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unsigned Rt = fieldFromInstruction(Insn, 12, 4);
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unsigned imm = fieldFromInstruction(Insn, 0, 8);
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imm |= (Rn << 9);
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if (Rn == 15) {
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switch (Inst.getOpcode()) {
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case ARM::t2LDRT:
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Inst.setOpcode(ARM::t2LDRpci);
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break;
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case ARM::t2LDRBT:
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Inst.setOpcode(ARM::t2LDRBpci);
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break;
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case ARM::t2LDRHT:
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Inst.setOpcode(ARM::t2LDRHpci);
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break;
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case ARM::t2LDRSBT:
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Inst.setOpcode(ARM::t2LDRSBpci);
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break;
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case ARM::t2LDRSHT:
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Inst.setOpcode(ARM::t2LDRSHpci);
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break;
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default:
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return MCDisassembler::Fail;
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}
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return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
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}
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if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
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return MCDisassembler::Fail;
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if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
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return MCDisassembler::Fail;
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return S;
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}
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static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void* Decoder) {
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DecodeStatus S = MCDisassembler::Success;
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unsigned Rt = fieldFromInstruction(Insn, 12, 4);
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unsigned U = fieldFromInstruction(Insn, 23, 1);
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int imm = fieldFromInstruction(Insn, 0, 12);
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// FIXME: detect and decode PLD properly
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if (Inst.getOpcode() == ARM::t2LDRBpci && Rt == 15) {
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Inst.setOpcode(ARM::t2PLDi12);
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Inst.addOperand(MCOperand::CreateReg(ARM::PC));
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} else {
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if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
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return MCDisassembler::Fail;
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}
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if (!U) {
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// Special case for #-0.
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if (imm == 0)
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imm = INT32_MIN;
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else
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imm = -imm;
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}
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Inst.addOperand(MCOperand::CreateImm(imm));
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return S;
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}
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static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder) {
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if (Val == 0)
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@ -3353,6 +3512,34 @@ static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
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addr |= Rn << 9;
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unsigned load = fieldFromInstruction(Insn, 20, 1);
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if (Rn == 15) {
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switch (Inst.getOpcode()) {
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case ARM::t2LDR_PRE:
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case ARM::t2LDR_POST:
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Inst.setOpcode(ARM::t2LDRpci);
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break;
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case ARM::t2LDRB_PRE:
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case ARM::t2LDRB_POST:
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Inst.setOpcode(ARM::t2LDRBpci);
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break;
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case ARM::t2LDRH_PRE:
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case ARM::t2LDRH_POST:
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Inst.setOpcode(ARM::t2LDRHpci);
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break;
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case ARM::t2LDRSB_PRE:
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case ARM::t2LDRSB_POST:
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Inst.setOpcode(ARM::t2LDRSBpci);
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break;
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case ARM::t2LDRSH_PRE:
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case ARM::t2LDRSH_POST:
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Inst.setOpcode(ARM::t2LDRSHpci);
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break;
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default:
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return MCDisassembler::Fail;
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}
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return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
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}
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if (!load) {
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if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
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return MCDisassembler::Fail;
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@ -315,15 +315,29 @@ void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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if (MO1.isExpr())
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if (MO1.isExpr()) {
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O << *MO1.getExpr();
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else if (MO1.isImm()) {
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O << markup("<mem:") << "[pc, "
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<< markup("<imm:") << "#" << formatImm(MO1.getImm())
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<< markup(">]>", "]");
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return;
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}
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else
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llvm_unreachable("Unknown LDR label operand?");
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O << markup("<mem:") << "[pc, ";
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int32_t OffImm = (int32_t)MO1.getImm();
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bool isSub = OffImm < 0;
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// Special value for #-0. All others are normal.
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if (OffImm == INT32_MIN)
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OffImm = 0;
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if (isSub) {
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O << markup("<imm:")
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<< "#-" << formatImm(-OffImm)
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<< markup(">");
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} else {
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O << markup("<imm:")
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<< "#" << formatImm(OffImm)
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<< markup(">");
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}
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O << "]" << markup(">");
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}
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// so_reg is a 4-operand unit corresponding to register forms of the A5.1
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@ -552,6 +552,17 @@
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0xd7 0xf8 0x01 0xf1
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#------------------------------------------------------------------------------
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# LDR(literal)
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#------------------------------------------------------------------------------
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# CHECK: ldr.w r4, [pc, #-0]
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# CHECK: ldr.w r2, [pc, #-40]
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# CHECK: ldr.w r1, [pc, #1024]
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0x5f 0xf8 0x00 0x40
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0x5f 0xf8 0x28 0x20
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0xdf 0xf8 0x00 0x14
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#------------------------------------------------------------------------------
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# LDR(register)
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#------------------------------------------------------------------------------
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@ -630,6 +641,17 @@
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0x1d 0xf8 0x04 0x39
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#------------------------------------------------------------------------------
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# LDRB(literal)
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#------------------------------------------------------------------------------
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# CHECK: ldrb.w r6, [pc, #-0]
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# CHECK: ldrb.w r10, [pc, #227]
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# CHECK: ldrb.w r5, [pc, #0]
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0x1f 0xf8 0x00 0x60
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0x9f 0xf8 0xe3 0xa0
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0x9f 0xf8 0x00 0x50
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#------------------------------------------------------------------------------
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# LDRBT
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#------------------------------------------------------------------------------
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@ -699,14 +721,12 @@
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# CHECK: ldrh.w r5, [r6, #33]
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# CHECK: ldrh.w r5, [r6, #257]
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# CHECK: ldrh.w lr, [r7, #257]
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# CHECK: ldrh.w r0, [pc, #-21]
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0x35 0xf8 0x04 0x5c
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0x35 0x8c
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0xb6 0xf8 0x21 0x50
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0xb6 0xf8 0x01 0x51
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0xb7 0xf8 0x01 0xe1
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0x3f 0xf8 0x15 0x00
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#------------------------------------------------------------------------------
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@ -739,6 +759,17 @@
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0x3d 0xf8 0x04 0x39
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#------------------------------------------------------------------------------
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# LDRH(literal)
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#------------------------------------------------------------------------------
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# CHECK: ldrh.w r7, [pc, #-0]
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# CHECK: ldrh.w r5, [pc, #121]
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# CHECK: ldrh.w r4, [pc, #0]
|
||||
0x3f 0xf8 0x00 0x70
|
||||
0xbf 0xf8 0x79 0x50
|
||||
0xbf 0xf8 0x00 0x40
|
||||
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# LDRSB(immediate)
|
||||
#------------------------------------------------------------------------------
|
||||
@ -785,6 +816,17 @@
|
||||
0x1d 0xf9 0x04 0x39
|
||||
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# LDRSB(literal)
|
||||
#------------------------------------------------------------------------------
|
||||
# CHECK: ldrsb.w r0, [pc, #-0]
|
||||
# CHECK: ldrsb.w r12, [pc, #80]
|
||||
# CHECK: ldrsb.w r3, [pc, #0]
|
||||
0x1f 0xf9 0x00 0x00
|
||||
0x9f 0xf9 0x50 0xc0
|
||||
0x9f 0xf9 0x00 0x30
|
||||
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# LDRSBT
|
||||
#------------------------------------------------------------------------------
|
||||
@ -846,6 +888,17 @@
|
||||
0x3d 0xf9 0x04 0x39
|
||||
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# LDRSH(literal)
|
||||
#------------------------------------------------------------------------------
|
||||
# CHECK: ldrsh.w r0, [pc, #-0]
|
||||
# CHECK: ldrsh.w r10, [pc, #-231]
|
||||
# CHECK: ldrsh.w r6, [pc, #0]
|
||||
0x3f 0xf9 0x00 0x00
|
||||
0x3f 0xf9 0xe7 0xa0
|
||||
0xbf 0xf9 0x00 0x60
|
||||
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# LDRSHT
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
Loading…
Reference in New Issue
Block a user