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Add, to constant islands, long jumps similar to ARM far branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195312 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -734,6 +734,7 @@ def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
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def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> {
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let hasDelaySlot = 0; // not true, but we add the nop for now
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let isCall=1;
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let Defs = [RA];
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}
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//
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@ -1399,9 +1399,29 @@ bool
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MipsConstantIslands::fixupUnconditionalBr(ImmBranch &Br) {
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MachineInstr *MI = Br.MI;
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MachineBasicBlock *MBB = MI->getParent();
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MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
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// Use BL to implement far jump.
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Br.MaxDisp = ((1 << 16)-1) * 2;
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MI->setDesc(TII->get(Mips::BimmX16));
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unsigned BimmX16MaxDisp = ((1 << 16)-1) * 2;
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if (isBBInRange(MI, DestBB, BimmX16MaxDisp)) {
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Br.MaxDisp = BimmX16MaxDisp;
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MI->setDesc(TII->get(Mips::BimmX16));
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}
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else {
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// need to give the math a more careful look here
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// this is really a segment address and not
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// a PC relative address. FIXME. But I think that
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// just reducing the bits by 1 as I've done is correct.
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// The basic block we are branching too much be longword aligned.
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// we know that RA is saved because we always save it right now.
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// this requirement will be relaxed later but we also have an alternate
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// way to implement this that I will implement that does not need jal.
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// We should have a way to back out this alignment restriction if we "can" later.
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// but it is not harmful.
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//
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DestBB->setAlignment(2);
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Br.MaxDisp = ((1<<24)-1) * 2;
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MI->setDesc(TII->get(Mips::Jal16));
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}
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BBInfo[MBB->getNumber()].Size += 2;
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adjustBBOffsetsAfter(MBB);
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HasFarJump = true;
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37
test/CodeGen/Mips/mbrsize4a.ll
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37
test/CodeGen/Mips/mbrsize4a.ll
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@ -0,0 +1,37 @@
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands < %s | FileCheck %s -check-prefix=jal16
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@j = global i32 10, align 4
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@.str = private unnamed_addr constant [11 x i8] c"at bottom\0A\00", align 1
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@i = common global i32 0, align 4
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; Function Attrs: nounwind
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define i32 @main() #0 {
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entry:
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%retval = alloca i32, align 4
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store i32 0, i32* %retval
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br label %z
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z: ; preds = %y, %entry
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%call = call i32 bitcast (i32 (...)* @foo to i32 ()*)()
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call void asm sideeffect ".space 10000000", ""() #2, !srcloc !1
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br label %y
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y: ; preds = %z
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%call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0))
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br label %z
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return: ; No predecessors!
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%0 = load i32* %retval
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ret i32 %0
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; jal16: jal $BB{{[0-9]+}}_{{[0-9]+}}
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}
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declare i32 @foo(...) #1
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declare i32 @printf(i8*, ...) #1
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #2 = { nounwind }
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!1 = metadata !{i32 68}
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