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* Doxygenify comments
* Fix spacing, grammar in comment * Make code layout consistent * Wrap code at 80 cols * Delete spurious blank lines No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14721 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman
parent
80b27ced2d
commit
ce22e76996
@ -71,32 +71,31 @@ MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
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MBB->push_back(this); // Add instruction to end of basic block!
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}
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///MachineInstr ctor - Copies MachineInstr arg exactly
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/// MachineInstr ctor - Copies MachineInstr arg exactly
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///
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MachineInstr::MachineInstr(const MachineInstr &MI) {
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Opcode = MI.getOpcode();
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numImplicitRefs = MI.getNumImplicitRefs();
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operands.reserve(MI.getNumOperands());
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//Add operands
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for(unsigned i=0; i < MI.getNumOperands(); ++i)
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// Add operands
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for (unsigned i = 0; i < MI.getNumOperands(); ++i)
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operands.push_back(MachineOperand(MI.getOperand(i)));
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//Set parent, next, and prev to null
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// Set parent, next, and prev to null
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parent = 0;
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prev = 0;
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next = 0;
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}
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MachineInstr::~MachineInstr()
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{
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MachineInstr::~MachineInstr() {
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LeakDetector::removeGarbageObject(this);
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}
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///clone - Create a copy of 'this' instruction that is identical in
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///all ways except the following: The instruction has no parent The
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///instruction has no name
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/// clone - Create a copy of 'this' instruction that is identical in all ways
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/// except the following: the new instruction has no parent and it has no name
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///
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MachineInstr* MachineInstr::clone() const {
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return new MachineInstr(*this);
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}
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@ -120,7 +119,6 @@ void MachineInstr::replace(short opcode, unsigned numOperands) {
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Opcode = opcode;
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operands.clear();
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operands.resize(numOperands, MachineOperand());
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}
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void MachineInstr::SetMachineOperandVal(unsigned i,
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@ -189,26 +187,25 @@ MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
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if (!defsOnly ||
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notDefsAndUses && (O.isDef() && !O.isUse()) ||
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!notDefsAndUses && O.isDef())
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{
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O.getMachineOperand().contents.value = newVal;
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++numSubst;
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}
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else
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{
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O.getMachineOperand().contents.value = newVal;
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++numSubst;
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} else
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someArgsWereIgnored = true;
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// Substitute implicit refs
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for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
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if (getImplicitRef(i) == oldVal)
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for (unsigned i = 0, N = getNumImplicitRefs(); i < N; ++i)
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if (getImplicitRef(i) == oldVal) {
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MachineOperand Op = getImplicitOp(i);
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if (!defsOnly ||
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notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) ||
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!notDefsAndUses && getImplicitOp(i).isDef())
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{
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getImplicitOp(i).contents.value = newVal;
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++numSubst;
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}
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else
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notDefsAndUses && (Op.isDef() && !Op.isUse()) ||
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!notDefsAndUses && Op.isDef())
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{
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Op.contents.value = newVal;
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++numSubst;
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} else
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someArgsWereIgnored = true;
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}
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return numSubst;
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}
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@ -218,9 +215,9 @@ void MachineInstr::dump() const {
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static inline std::ostream& OutputValue(std::ostream &os, const Value* val) {
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os << "(val ";
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os << (void*) val; // print address always
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os << (void*) val; // print address always
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if (val && val->hasName())
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os << " " << val->getName(); // print name also, if available
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os << " " << val->getName(); // print name also, if available
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os << ")";
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return os;
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}
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@ -238,12 +235,9 @@ static inline void OutputReg(std::ostream &os, unsigned RegNo,
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static void print(const MachineOperand &MO, std::ostream &OS,
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const TargetMachine *TM) {
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const MRegisterInfo *MRI = 0;
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if(TM)
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MRI = TM->getRegisterInfo();
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const MRegisterInfo *MRI = 0;
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if (TM) MRI = TM->getRegisterInfo();
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bool CloseParen = true;
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if (MO.isHiBits32())
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@ -331,9 +325,9 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
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++StartOp; // Don't print this operand again!
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}
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//Must check if Target machine is not null because machine BB could not
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//be attached to a Machine function yet
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if(TM)
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// Must check if Target machine is not null because machine BB could not
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// be attached to a Machine function yet
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if (TM)
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OS << TM->getInstrInfo()->getName(getOpcode());
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for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
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@ -353,14 +347,14 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
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// code for printing implicit references
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if (getNumImplicitRefs()) {
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OS << "\tImplicitRefs: ";
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for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
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for (unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
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OS << "\t";
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OutputValue(OS, getImplicitRef(i));
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if (getImplicitOp(i).isDef())
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if (getImplicitOp(i).isUse())
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OS << "<def&use>";
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else
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OS << "<def>";
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if (getImplicitOp(i).isUse())
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OS << "<def&use>";
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else
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OS << "<def>";
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}
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}
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@ -373,7 +367,7 @@ std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
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// info for the instruction.
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if (const MachineBasicBlock *MBB = MI.getParent()) {
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const MachineFunction *MF = MBB->getParent();
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if(MF)
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if (MF)
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MI.print(os, &MF->getTarget());
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else
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MI.print(os, 0);
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@ -384,7 +378,7 @@ std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
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// and such.
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os << TargetInstrDescriptors[MI.getOpcode()].Name;
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for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
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for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) {
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os << "\t" << MI.getOperand(i);
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if (MI.getOperand(i).isDef())
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if (MI.getOperand(i).isUse())
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@ -397,7 +391,7 @@ std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
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unsigned NumOfImpRefs = MI.getNumImplicitRefs();
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if (NumOfImpRefs > 0) {
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os << "\tImplicit: ";
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for (unsigned z=0; z < NumOfImpRefs; z++) {
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for (unsigned z = 0; z < NumOfImpRefs; z++) {
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OutputValue(os, MI.getImplicitRef(z));
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if (MI.getImplicitOp(z).isDef())
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if (MI.getImplicitOp(z).isUse())
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@ -421,68 +415,66 @@ std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
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else if (MO.isLoBits64())
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OS << "%hm(";
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switch (MO.getType())
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{
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case MachineOperand::MO_VirtualRegister:
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if (MO.hasAllocatedReg())
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OutputReg(OS, MO.getReg());
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switch (MO.getType()) {
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case MachineOperand::MO_VirtualRegister:
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if (MO.hasAllocatedReg())
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OutputReg(OS, MO.getReg());
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if (MO.getVRegValue()) {
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if (MO.hasAllocatedReg()) OS << "==";
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OS << "%vreg";
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OutputValue(OS, MO.getVRegValue());
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}
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break;
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case MachineOperand::MO_CCRegister:
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OS << "%ccreg";
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if (MO.getVRegValue()) {
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if (MO.hasAllocatedReg()) OS << "==";
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OS << "%vreg";
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OutputValue(OS, MO.getVRegValue());
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if (MO.hasAllocatedReg()) {
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OS << "==";
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OutputReg(OS, MO.getReg());
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}
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break;
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case MachineOperand::MO_MachineRegister:
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OutputReg(OS, MO.getMachineRegNum());
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break;
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case MachineOperand::MO_SignExtendedImmed:
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OS << (long)MO.getImmedValue();
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break;
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case MachineOperand::MO_UnextendedImmed:
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OS << (long)MO.getImmedValue();
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break;
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case MachineOperand::MO_PCRelativeDisp:
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{
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const Value* opVal = MO.getVRegValue();
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bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
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OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
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if (opVal->hasName())
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OS << opVal->getName();
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else
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OS << (const void*) opVal;
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OS << ")";
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break;
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}
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case MachineOperand::MO_MachineBasicBlock:
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OS << "<mbb:"
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<< ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
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<< "@" << (void*)MO.getMachineBasicBlock() << ">";
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break;
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case MachineOperand::MO_FrameIndex:
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OS << "<fi#" << MO.getFrameIndex() << ">";
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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OS << "<cp#" << MO.getConstantPoolIndex() << ">";
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break;
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case MachineOperand::MO_GlobalAddress:
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OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
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break;
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case MachineOperand::MO_ExternalSymbol:
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OS << "<es:" << MO.getSymbolName() << ">";
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break;
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default:
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assert(0 && "Unrecognized operand type");
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break;
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}
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break;
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case MachineOperand::MO_CCRegister:
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OS << "%ccreg";
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OutputValue(OS, MO.getVRegValue());
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if (MO.hasAllocatedReg()) {
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OS << "==";
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OutputReg(OS, MO.getReg());
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}
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break;
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case MachineOperand::MO_MachineRegister:
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OutputReg(OS, MO.getMachineRegNum());
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break;
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case MachineOperand::MO_SignExtendedImmed:
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OS << (long)MO.getImmedValue();
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break;
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case MachineOperand::MO_UnextendedImmed:
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OS << (long)MO.getImmedValue();
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break;
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case MachineOperand::MO_PCRelativeDisp: {
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const Value* opVal = MO.getVRegValue();
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bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
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OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
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if (opVal->hasName())
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OS << opVal->getName();
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else
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OS << (const void*) opVal;
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OS << ")";
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break;
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}
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case MachineOperand::MO_MachineBasicBlock:
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OS << "<mbb:"
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<< ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
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<< "@" << (void*)MO.getMachineBasicBlock() << ">";
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break;
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case MachineOperand::MO_FrameIndex:
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OS << "<fi#" << MO.getFrameIndex() << ">";
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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OS << "<cp#" << MO.getConstantPoolIndex() << ">";
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break;
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case MachineOperand::MO_GlobalAddress:
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OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
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break;
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case MachineOperand::MO_ExternalSymbol:
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OS << "<es:" << MO.getSymbolName() << ">";
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break;
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default:
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assert(0 && "Unrecognized operand type");
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break;
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}
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if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64())
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OS << ")";
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