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Add XOP feature flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145682 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -91,6 +91,8 @@ def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true",
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"Enable three-operand fused multiple-add">;
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"Enable three-operand fused multiple-add">;
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def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
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def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
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"Enable four-operand fused multiple-add">;
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"Enable four-operand fused multiple-add">;
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def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
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"Enable XOP instructions">;
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def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
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def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
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"HasVectorUAMem", "true",
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"HasVectorUAMem", "true",
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"Allow unaligned memory operands on vector/SIMD instructions">;
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"Allow unaligned memory operands on vector/SIMD instructions">;
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@@ -199,10 +201,11 @@ def : Proc<"amdfam10", [FeatureSSE3, FeatureSSE4A,
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// FIXME: Disabling AVX for now since it's not ready.
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// FIXME: Disabling AVX for now since it's not ready.
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def : Proc<"bdver1", [FeatureSSE42, FeatureSSE4A, FeatureCMPXCHG16B,
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def : Proc<"bdver1", [FeatureSSE42, FeatureSSE4A, FeatureCMPXCHG16B,
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FeatureAES, FeatureCLMUL, FeatureFMA4,
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FeatureAES, FeatureCLMUL, FeatureFMA4,
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FeatureLZCNT]>;
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FeatureXOP, FeatureLZCNT]>;
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def : Proc<"bdver2", [FeatureSSE42, FeatureSSE4A, FeatureCMPXCHG16B,
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def : Proc<"bdver2", [FeatureSSE42, FeatureSSE4A, FeatureCMPXCHG16B,
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FeatureAES, FeatureCLMUL, FeatureFMA4,
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FeatureAES, FeatureCLMUL, FeatureFMA4,
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FeatureF16C, FeatureLZCNT, FeatureBMI]>;
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FeatureXOP, FeatureF16C, FeatureLZCNT,
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FeatureBMI]>;
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def : Proc<"winchip-c6", [FeatureMMX]>;
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def : Proc<"winchip-c6", [FeatureMMX]>;
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def : Proc<"winchip2", [Feature3DNow]>;
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def : Proc<"winchip2", [Feature3DNow]>;
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@@ -273,6 +273,8 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
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if (IsAMD && ((ECX >> 16) & 0x1)) {
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if (IsAMD && ((ECX >> 16) & 0x1)) {
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HasFMA4 = true;
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HasFMA4 = true;
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ToggleFeature(X86::FeatureFMA4);
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ToggleFeature(X86::FeatureFMA4);
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HasXOP = true;
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ToggleFeature(X86::FeatureXOP);
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}
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}
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}
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}
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}
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}
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@@ -317,6 +319,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
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, HasCLMUL(false)
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, HasCLMUL(false)
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, HasFMA3(false)
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, HasFMA3(false)
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, HasFMA4(false)
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, HasFMA4(false)
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, HasXOP(false)
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, HasMOVBE(false)
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, HasMOVBE(false)
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, HasRDRAND(false)
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, HasRDRAND(false)
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, HasF16C(false)
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, HasF16C(false)
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@@ -93,6 +93,9 @@ protected:
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/// HasFMA4 - Target has 4-operand fused multiply-add
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/// HasFMA4 - Target has 4-operand fused multiply-add
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bool HasFMA4;
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bool HasFMA4;
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/// HasXOP - Target has XOP instructions
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bool HasXOP;
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/// HasMOVBE - True if the processor has the MOVBE instruction.
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/// HasMOVBE - True if the processor has the MOVBE instruction.
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bool HasMOVBE;
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bool HasMOVBE;
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@@ -198,6 +201,7 @@ public:
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bool hasCLMUL() const { return HasCLMUL; }
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bool hasCLMUL() const { return HasCLMUL; }
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bool hasFMA3() const { return HasFMA3; }
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bool hasFMA3() const { return HasFMA3; }
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bool hasFMA4() const { return HasFMA4; }
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bool hasFMA4() const { return HasFMA4; }
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bool hasXOP() const { return HasXOP; }
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bool hasMOVBE() const { return HasMOVBE; }
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bool hasMOVBE() const { return HasMOVBE; }
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bool hasRDRAND() const { return HasRDRAND; }
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bool hasRDRAND() const { return HasRDRAND; }
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bool hasF16C() const { return HasF16C; }
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bool hasF16C() const { return HasF16C; }
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