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Make x86 test actually test x86 code generation. Fix the

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construct on ARM, which was breaking by coincidence, and add a similar 
testcase for ARM.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79719 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman
2009-08-22 03:13:10 +00:00
parent b8b85cfd4d
commit ce392eb3ea
3 changed files with 15 additions and 4 deletions
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4
test/CodeGen/X86/vshift_split.ll
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@@ -1,8 +1,8 @@
; RUN: llvm-as < %s | llc
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
; Example that requires splitting and expanding a vector shift.
define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
entry:
%shr = lshr <2 x i64> %val, < i64 2, i64 2 > ; <<2 x i64>> [#uses=1]
%shr = lshr <2 x i64> %val, < i64 2, i64 3 >
ret <2 x i64> %shr
}