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Remove uses of getCalleeSavedRegClasses from outside the

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backends and removes the virtual declaration. With that out of the way
I should be able to cleanup one backend at a time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105321 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2010-06-02 12:39:06 +00:00
parent 8dbbacedcd
commit ce48c1de82
3 changed files with 26 additions and 12 deletions
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9
include/llvm/Target/TargetRegisterInfo.h
View File

@ -319,6 +319,10 @@ public:
virtual const TargetRegisterClass *
getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const;
/// getMinimalPhysRegClass - Returns the Register Class of a physical
/// register of the given type.
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg) const;
/// getAllocatableSet - Returns a bitset indexed by register number
/// indicating if a register is allocatable or not. If a register class is
/// specified, returns the subset for the class.
@ -438,11 +442,6 @@ public:
virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
const = 0;
/// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
/// register classes to spill each callee saved register with. The order and
/// length of this list match the getCalleeSaveRegs() list.
virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
const MachineFunction *MF) const =0;
/// getReservedRegs - Returns a bitset indexed by physical register number
/// indicating if a register is a special register that has particular uses

10
lib/CodeGen/PrologEpilogInserter.cpp
View File

@ -202,22 +202,18 @@ void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) {
if (Fn.getFunction()->hasFnAttr(Attribute::Naked))
return;
// Figure out which *callee saved* registers are modified by the current
// function, thus needing to be saved and restored in the prolog/epilog.
const TargetRegisterClass * const *CSRegClasses =
RegInfo->getCalleeSavedRegClasses(&Fn);
std::vector<CalleeSavedInfo> CSI;
for (unsigned i = 0; CSRegs[i]; ++i) {
unsigned Reg = CSRegs[i];
const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
if (Fn.getRegInfo().isPhysRegUsed(Reg)) {
// If the reg is modified, save it!
CSI.push_back(CalleeSavedInfo(Reg, CSRegClasses[i]));
CSI.push_back(CalleeSavedInfo(Reg, RC));
} else {
for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
*AliasSet; ++AliasSet) { // Check alias registers too.
if (Fn.getRegInfo().isPhysRegUsed(*AliasSet)) {
CSI.push_back(CalleeSavedInfo(Reg, CSRegClasses[i]));
CSI.push_back(CalleeSavedInfo(Reg, RC));
break;
}
}

19
lib/Target/TargetRegisterInfo.cpp
View File

@ -60,6 +60,25 @@ TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, EVT VT) const {
return BestRC;
}
/// getMinimalPhysRegClass - Returns the Register Class of a physical
/// register of the given type.
const TargetRegisterClass *
TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg) const {
assert(isPhysicalRegister(reg) && "reg must be a physical register");
// Pick the most sub register class of the right type that contains
// this physreg.
const TargetRegisterClass* BestRC = 0;
for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
const TargetRegisterClass* RC = *I;
if (RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC)))
BestRC = RC;
}
assert(BestRC && "Couldn't find the register class");
return BestRC;
}
/// getAllocatableSetForRC - Toggle the bits that represent allocatable
/// registers for the specific register class.
static void getAllocatableSetForRC(const MachineFunction &MF,