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ARM: thumb stores cannot use PC as dest register

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184179 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Amaury de la Vieuville
2013-06-18 08:02:56 +00:00
parent 88f34b50d4
commit cea0032f73
2 changed files with 74 additions and 0 deletions
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37
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -3164,6 +3164,17 @@ static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
unsigned Rm = fieldFromInstruction(Val, 2, 4);
unsigned imm = fieldFromInstruction(Val, 0, 2);
// Thumb stores cannot use PC as dest register.
switch (Inst.getOpcode()) {
case ARM::t2STRHs:
case ARM::t2STRBs:
case ARM::t2STRs:
if (Rn == 15)
return MCDisassembler::Fail;
default:
break;
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
@ -3292,6 +3303,21 @@ static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
unsigned Rn = fieldFromInstruction(Val, 9, 4);
unsigned imm = fieldFromInstruction(Val, 0, 9);
// Thumb stores cannot use PC as dest register.
switch (Inst.getOpcode()) {
case ARM::t2STRT:
case ARM::t2STRBT:
case ARM::t2STRHT:
case ARM::t2STRi8:
case ARM::t2STRHi8:
case ARM::t2STRBi8:
if (Rn == 15)
return MCDisassembler::Fail;
break;
default:
break;
}
// Some instructions always use an additive offset.
switch (Inst.getOpcode()) {
case ARM::t2LDRT:
@ -3353,6 +3379,17 @@ static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
unsigned Rn = fieldFromInstruction(Val, 13, 4);
unsigned imm = fieldFromInstruction(Val, 0, 12);
// Thumb stores cannot use PC as dest register.
switch (Inst.getOpcode()) {
case ARM::t2STRi12:
case ARM::t2STRBi12:
case ARM::t2STRHi12:
if (Rn == 15)
return MCDisassembler::Fail;
default:
break;
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(imm));