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Place context in member variables instead of passing around pointers.
Use the opportunity to get rid of the trailing underscore variable names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127618 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -18,14 +18,20 @@ namespace llvm {
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class MachineInstr;
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class TargetInstrInfo;
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class TargetRegisterInfo;
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class MachineRegisterInfo;
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class LiveVariables;
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/// Process IMPLICIT_DEF instructions and make sure there is one implicit_def
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/// for each use. Add isUndef marker to implicit_def defs and their uses.
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class ProcessImplicitDefs : public MachineFunctionPass {
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private:
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineRegisterInfo *MRI;
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LiveVariables *LV;
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bool CanTurnIntoImplicitDef(MachineInstr *MI, unsigned Reg,
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unsigned OpIdx, const TargetInstrInfo *tii_,
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unsigned OpIdx,
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SmallSet<unsigned, 8> &ImpDefRegs);
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public:
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@ -47,7 +47,6 @@ void ProcessImplicitDefs::getAnalysisUsage(AnalysisUsage &AU) const {
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bool
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ProcessImplicitDefs::CanTurnIntoImplicitDef(MachineInstr *MI,
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unsigned Reg, unsigned OpIdx,
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const TargetInstrInfo *tii_,
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SmallSet<unsigned, 8> &ImpDefRegs) {
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switch(OpIdx) {
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case 1:
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@ -61,7 +60,6 @@ ProcessImplicitDefs::CanTurnIntoImplicitDef(MachineInstr *MI,
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}
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static bool isUndefCopy(MachineInstr *MI, unsigned Reg,
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const TargetInstrInfo *tii_,
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SmallSet<unsigned, 8> &ImpDefRegs) {
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if (MI->isCopy()) {
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MachineOperand &MO0 = MI->getOperand(0);
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@ -86,11 +84,10 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
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bool Changed = false;
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const TargetInstrInfo *tii_ = fn.getTarget().getInstrInfo();
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const TargetRegisterInfo *tri_ = fn.getTarget().getRegisterInfo();
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MachineRegisterInfo *mri_ = &fn.getRegInfo();
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LiveVariables *lv_ = &getAnalysis<LiveVariables>();
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TII = fn.getTarget().getInstrInfo();
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TRI = fn.getTarget().getRegisterInfo();
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MRI = &fn.getRegInfo();
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LV = &getAnalysis<LiveVariables>();
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SmallSet<unsigned, 8> ImpDefRegs;
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SmallVector<MachineInstr*, 8> ImpDefMIs;
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@ -113,7 +110,7 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
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unsigned Reg = MI->getOperand(0).getReg();
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ImpDefRegs.insert(Reg);
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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for (const unsigned *SS = tri_->getSubRegisters(Reg); *SS; ++SS)
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for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS)
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ImpDefRegs.insert(*SS);
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}
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ImpDefMIs.push_back(MI);
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@ -125,7 +122,7 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
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MachineOperand &MO = MI->getOperand(1);
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if (MO.isUndef() || ImpDefRegs.count(MO.getReg())) {
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if (MO.isKill()) {
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LiveVariables::VarInfo& vi = lv_->getVarInfo(MO.getReg());
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LiveVariables::VarInfo& vi = LV->getVarInfo(MO.getReg());
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vi.removeKill(MI);
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}
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MI->eraseFromParent();
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@ -145,14 +142,14 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
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if (!ImpDefRegs.count(Reg))
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continue;
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// Use is a copy, just turn it into an implicit_def.
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if (CanTurnIntoImplicitDef(MI, Reg, i, tii_, ImpDefRegs)) {
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if (CanTurnIntoImplicitDef(MI, Reg, i, ImpDefRegs)) {
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bool isKill = MO.isKill();
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MI->setDesc(tii_->get(TargetOpcode::IMPLICIT_DEF));
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MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
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for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
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MI->RemoveOperand(j);
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if (isKill) {
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ImpDefRegs.erase(Reg);
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LiveVariables::VarInfo& vi = lv_->getVarInfo(Reg);
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LiveVariables::VarInfo& vi = LV->getVarInfo(Reg);
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vi.removeKill(MI);
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}
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ChangedToImpDef = true;
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@ -210,8 +207,8 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
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// uses.
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bool Skip = false;
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SmallVector<MachineInstr*, 4> DeadImpDefs;
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for (MachineRegisterInfo::def_iterator DI = mri_->def_begin(Reg),
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DE = mri_->def_end(); DI != DE; ++DI) {
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for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(Reg),
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DE = MRI->def_end(); DI != DE; ++DI) {
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MachineInstr *DeadImpDef = &*DI;
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if (!DeadImpDef->isImplicitDef()) {
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Skip = true;
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@ -229,8 +226,8 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
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Changed = true;
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// Process each use instruction once.
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for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
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UE = mri_->use_end(); UI != UE; ++UI) {
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for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
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UE = MRI->use_end(); UI != UE; ++UI) {
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if (UI.getOperand().isUndef())
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continue;
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MachineInstr *RMI = &*UI;
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@ -242,8 +239,8 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
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MachineInstr *RMI = RUses[i];
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// Turn a copy use into an implicit_def.
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if (isUndefCopy(RMI, Reg, tii_, ImpDefRegs)) {
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RMI->setDesc(tii_->get(TargetOpcode::IMPLICIT_DEF));
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if (isUndefCopy(RMI, Reg, ImpDefRegs)) {
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RMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
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bool isKill = false;
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SmallVector<unsigned, 4> Ops;
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@ -263,15 +260,15 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
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// Update LiveVariables varinfo if the instruction is a kill.
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if (isKill) {
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LiveVariables::VarInfo& vi = lv_->getVarInfo(Reg);
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LiveVariables::VarInfo& vi = LV->getVarInfo(Reg);
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vi.removeKill(RMI);
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}
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continue;
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}
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// Replace Reg with a new vreg that's marked implicit.
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const TargetRegisterClass* RC = mri_->getRegClass(Reg);
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unsigned NewVReg = mri_->createVirtualRegister(RC);
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const TargetRegisterClass* RC = MRI->getRegClass(Reg);
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unsigned NewVReg = MRI->createVirtualRegister(RC);
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bool isKill = true;
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for (unsigned j = 0, ee = RMI->getNumOperands(); j != ee; ++j) {
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MachineOperand &RRMO = RMI->getOperand(j);
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