6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-18 12:29:21 +00:00
Code Issues Projects Releases Wiki Activity

Fix Regression/CodeGen/X86/inline-asm.ll, a case where inline asm causes

Browse Source 
implement extension of a register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28731 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-06-08 18:22:48 +00:00
parent 5591c5183b
commit cf752aa502
1 changed files with 13 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -1780,15 +1780,19 @@ SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
}
// Otherwise, if the return value was promoted, truncate it to the
// Otherwise, if the return value was promoted or extended, truncate it to the
// appropriate type.
if (RegVT == ValueVT)
return Val;
if (MVT::isInteger(RegVT))
return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
else
if (MVT::isInteger(RegVT)) {
if (ValueVT < RegVT)
return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
else
return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
} else {
return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
}
}
/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
@ -1895,14 +1899,17 @@ GetRegistersForValue(const std::string &ConstrCode,
if (PhysReg.first) {
if (VT == MVT::Other)
ValueVT = *PhysReg.second->vt_begin();
RegVT = VT;
// Get the actual register value type. This is important, because the user
// may have asked for (e.g.) the AX register in i32 type. We need to
// remember that AX is actually i16 to get the right extension.
RegVT = *PhysReg.second->vt_begin();
// This is a explicit reference to a physical register.
Regs.push_back(PhysReg.first);
// If this is an expanded reference, add the rest of the regs to Regs.
if (NumRegs != 1) {
RegVT = *PhysReg.second->vt_begin();
TargetRegisterClass::iterator I = PhysReg.second->begin();
TargetRegisterClass::iterator E = PhysReg.second->end();
for (; *I != PhysReg.first; ++I)