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start to clean up buildMI calls in mips fast-isel

Browse Source 
Summary: Merge branch 'master' into 1758_6

Test Plan:
No functionality change. Run "make check" and run test-suite.
Because our servers are not yet running again I have not yet run test-suite.
I will further review myself before submission.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3819

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210413 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler 2014-06-08 03:04:42 +00:00
parent 2aa472f4bd
commit cf7742cb63
1 changed files with 24 additions and 26 deletions
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50
lib/Target/Mips/MipsFastISel.cpp
View File

@ -83,7 +83,7 @@ private:
unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
// for some reason, this default is not generated by tablegen
// so we explicitly generate it here.
// so we explicitly generate it here.
//
unsigned FastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
unsigned Op0, bool Op0IsKill, uint64_t imm1,
@ -91,6 +91,20 @@ private:
return 0;
}
MachineInstrBuilder EmitInst(unsigned Opc) {
return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
}
MachineInstrBuilder EmitInst(unsigned Opc, unsigned DstReg) {
return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
DstReg);
}
MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg,
unsigned MemReg, int64_t MemOffset) {
return EmitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
}
#include "MipsGenFastISel.inc"
};
@ -155,10 +169,7 @@ bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
//
if (VT != MVT::i32)
return false;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::SW))
.addReg(SrcReg)
.addReg(Addr.Base.Reg)
.addImm(Addr.Offset);
EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset);
return true;
}
@ -198,8 +209,7 @@ bool MipsFastISel::SelectRet(const Instruction *I) {
if (Ret->getNumOperands() > 0) {
return false;
}
unsigned RetOpc = Mips::RetRA;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(RetOpc));
EmitInst(Mips::RetRA);
return true;
}
@ -233,9 +243,8 @@ unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) {
// TLS not supported at this time.
if (IsThreadLocal)
return 0;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LW), DestReg)
.addReg(MFI->getGlobalBaseReg())
.addGlobalAddress(GV, 0, MipsII::MO_GOT);
EmitInst(Mips::LW, DestReg).addReg(MFI->getGlobalBaseReg()).addGlobalAddress(
GV, 0, MipsII::MO_GOT);
return DestReg;
}
unsigned MipsFastISel::MaterializeInt(const Constant *C, MVT VT) {
@ -257,15 +266,10 @@ unsigned MipsFastISel::Materialize32BitInt(int64_t Imm,
if (isInt<16>(Imm)) {
unsigned Opc = Mips::ADDiu;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
.addReg(Mips::ZERO)
.addImm(Imm);
EmitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
return ResultReg;
} else if (isUInt<16>(Imm)) {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::ORi),
ResultReg)
.addReg(Mips::ZERO)
.addImm(Imm);
EmitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
return ResultReg;
}
unsigned Lo = Imm & 0xFFFF;
@ -273,16 +277,10 @@ unsigned MipsFastISel::Materialize32BitInt(int64_t Imm,
if (Lo) {
// Both Lo and Hi have nonzero bits.
unsigned TmpReg = createResultReg(RC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LUi),
TmpReg).addImm(Hi);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::ORi),
ResultReg)
.addReg(TmpReg)
.addImm(Lo);
EmitInst(Mips::LUi, TmpReg).addImm(Hi);
EmitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
} else {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LUi),
ResultReg).addImm(Hi);
EmitInst(Mips::LUi, ResultReg).addImm(Hi);
}
return ResultReg;
}