mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
[PowerPC] Print all inline-asm consts as signed numbers
Almost all immediates in PowerPC assembly (both 32-bit and 64-bit) are signed numbers, and it is important that we print them as such. To make sure that happens, we change PPCTargetLowering::LowerAsmOperandForConstraint so that it does all intermediate checks on a signed-extended int64_t value, and then creates the resulting target constant using MVT::i64. This will ensure that all negative values are printed as negative values (mirroring what is done in other backends to achieve the same sign-extension effect). This came up in the context of inline assembly like this: "add%I2 %0,%0,%2", ..., "Ir"(-1ll) where we used to print: addi 3,3,4294967295 and gcc would print: addi 3,3,-1 and gas accepts both forms, but our builtin assembler (correctly) does not. Now we print -1 like gcc does. While here, I replaced a bunch of custom integer checks with isInt<16> and friends from MathExtras.h. Thanks to Paul Hargrove for the bug report. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223220 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
10cae8e352
commit
cf988bca67
@ -8987,37 +8987,42 @@ void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
|
|||||||
case 'P': {
|
case 'P': {
|
||||||
ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
|
ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
|
||||||
if (!CST) return; // Must be an immediate to match.
|
if (!CST) return; // Must be an immediate to match.
|
||||||
unsigned Value = CST->getZExtValue();
|
int64_t Value = CST->getSExtValue();
|
||||||
|
EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
|
||||||
|
// numbers are printed as such.
|
||||||
switch (Letter) {
|
switch (Letter) {
|
||||||
default: llvm_unreachable("Unknown constraint letter!");
|
default: llvm_unreachable("Unknown constraint letter!");
|
||||||
case 'I': // "I" is a signed 16-bit constant.
|
case 'I': // "I" is a signed 16-bit constant.
|
||||||
if ((short)Value == (int)Value)
|
if (isInt<16>(Value))
|
||||||
Result = DAG.getTargetConstant(Value, Op.getValueType());
|
Result = DAG.getTargetConstant(Value, TCVT);
|
||||||
break;
|
break;
|
||||||
case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
|
case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
|
||||||
|
if (isShiftedUInt<16, 16>(Value))
|
||||||
|
Result = DAG.getTargetConstant(Value, TCVT);
|
||||||
|
break;
|
||||||
case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
|
case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
|
||||||
if ((short)Value == 0)
|
if (isShiftedInt<16, 16>(Value))
|
||||||
Result = DAG.getTargetConstant(Value, Op.getValueType());
|
Result = DAG.getTargetConstant(Value, TCVT);
|
||||||
break;
|
break;
|
||||||
case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
|
case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
|
||||||
if ((Value >> 16) == 0)
|
if (isUInt<16>(Value))
|
||||||
Result = DAG.getTargetConstant(Value, Op.getValueType());
|
Result = DAG.getTargetConstant(Value, TCVT);
|
||||||
break;
|
break;
|
||||||
case 'M': // "M" is a constant that is greater than 31.
|
case 'M': // "M" is a constant that is greater than 31.
|
||||||
if (Value > 31)
|
if (Value > 31)
|
||||||
Result = DAG.getTargetConstant(Value, Op.getValueType());
|
Result = DAG.getTargetConstant(Value, TCVT);
|
||||||
break;
|
break;
|
||||||
case 'N': // "N" is a positive constant that is an exact power of two.
|
case 'N': // "N" is a positive constant that is an exact power of two.
|
||||||
if ((int)Value > 0 && isPowerOf2_32(Value))
|
if (Value > 0 && isPowerOf2_64(Value))
|
||||||
Result = DAG.getTargetConstant(Value, Op.getValueType());
|
Result = DAG.getTargetConstant(Value, TCVT);
|
||||||
break;
|
break;
|
||||||
case 'O': // "O" is the constant zero.
|
case 'O': // "O" is the constant zero.
|
||||||
if (Value == 0)
|
if (Value == 0)
|
||||||
Result = DAG.getTargetConstant(Value, Op.getValueType());
|
Result = DAG.getTargetConstant(Value, TCVT);
|
||||||
break;
|
break;
|
||||||
case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
|
case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
|
||||||
if ((short)-Value == (int)-Value)
|
if (isInt<16>(-Value))
|
||||||
Result = DAG.getTargetConstant(Value, Op.getValueType());
|
Result = DAG.getTargetConstant(Value, TCVT);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
25
test/CodeGen/PowerPC/ia-neg-const.ll
Normal file
25
test/CodeGen/PowerPC/ia-neg-const.ll
Normal file
@ -0,0 +1,25 @@
|
|||||||
|
; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
|
||||||
|
target datalayout = "E-m:e-i64:64-n32:64"
|
||||||
|
target triple = "powerpc64-unknown-linux-gnu"
|
||||||
|
|
||||||
|
@.str = private unnamed_addr constant [5 x i8] c"%ld\0A\00", align 1
|
||||||
|
|
||||||
|
; Function Attrs: nounwind
|
||||||
|
define i64 @main() #0 {
|
||||||
|
entry:
|
||||||
|
%x = alloca i64, align 8
|
||||||
|
store i64 0, i64* %x, align 8
|
||||||
|
%0 = call i64 asm sideeffect "ld $0,$1\0A\09add${2:I} $0,$0,$2", "=&r,*m,Ir"(i64* %x, i64 -1) #0
|
||||||
|
ret i64 %0
|
||||||
|
}
|
||||||
|
|
||||||
|
; CHECK: ld
|
||||||
|
; CHECK-NOT: addi 3,3,4294967295
|
||||||
|
; CHECK: addi 3,3,-1
|
||||||
|
; CHECK: blr
|
||||||
|
|
||||||
|
; Function Attrs: nounwind
|
||||||
|
declare signext i32 @printf(i8* nocapture readonly, ...) #0
|
||||||
|
|
||||||
|
attributes #0 = { nounwind }
|
||||||
|
|
Loading…
Reference in New Issue
Block a user