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Add 8-bit regclass and pattern for sext_inreg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70721 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
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commit
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@ -14,7 +14,7 @@
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//===----------------------------------------------------------------------===//
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def RetCC_MSP430 : CallingConv<[
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// i16 are returned in registers R15, R14, R13, R12
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CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>
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CCIfType<[i16], CCAssignToReg<[R15W, R14W, R13W, R12W]>>
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]>;
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//===----------------------------------------------------------------------===//
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@ -26,7 +26,7 @@ def CC_MSP430 : CallingConv<[
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// The first 4 integer arguments of non-varargs functions are passed in
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// integer registers.
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CCIfNotVarArg<CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>>,
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CCIfNotVarArg<CCIfType<[i16], CCAssignToReg<[R15W, R14W, R13W, R12W]>>>,
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// Integer values get stored in stack slots that are 2 bytes in
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// size and 2-byte aligned.
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@ -69,89 +69,95 @@ def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
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let isTwoAddress = 1 in {
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let Defs = [SR] in {
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let Defs = [SRW] in {
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let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
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// FIXME: Provide proper encoding!
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def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"add.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
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(implicit SR)]>;
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(implicit SRW)]>;
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}
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def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"add.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (add GR16:$src1, imm:$src2)),
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(implicit SR)]>;
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(implicit SRW)]>;
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let Uses = [SR] in {
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let Uses = [SRW] in {
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let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
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def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"addc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
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(implicit SR)]>;
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(implicit SRW)]>;
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} // isCommutable
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def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"addc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
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(implicit SR)]>;
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(implicit SRW)]>;
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}
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let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
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def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"and.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
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(implicit SR)]>;
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(implicit SRW)]>;
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}
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def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"and.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (and GR16:$src1, imm:$src2)),
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(implicit SR)]>;
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(implicit SRW)]>;
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let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
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def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"xor.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
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(implicit SR)]>;
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(implicit SRW)]>;
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}
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def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"xor.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
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(implicit SR)]>;
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(implicit SRW)]>;
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def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"sub.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
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(implicit SR)]>;
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(implicit SRW)]>;
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def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"sub.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
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(implicit SR)]>;
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(implicit SRW)]>;
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let Uses = [SR] in {
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let Uses = [SRW] in {
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def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"subc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
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(implicit SR)]>;
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(implicit SRW)]>;
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def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"subc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
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(implicit SR)]>;
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(implicit SRW)]>;
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}
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// FIXME: Provide proper encoding!
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def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
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"rra.w\t$dst",
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[(set GR16:$dst, (MSP430rra GR16:$src)),
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(implicit SR)]>;
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} // Defs = [SR]
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(implicit SRW)]>;
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def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
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"sxt\t$dst",
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[(set GR16:$dst, (sext_inreg GR16:$src, i8)),
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(implicit SRW)]>;
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} // Defs = [SRW]
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let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
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def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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@ -31,8 +31,8 @@ MSP430RegisterInfo::MSP430RegisterInfo(const TargetInstrInfo &tii)
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const unsigned*
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MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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static const unsigned CalleeSavedRegs[] = {
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MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7,
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MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
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MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
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MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
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0
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};
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@ -57,14 +57,14 @@ MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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// Mark 4 special registers as reserved.
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Reserved.set(MSP430::PC);
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Reserved.set(MSP430::SP);
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Reserved.set(MSP430::SR);
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Reserved.set(MSP430::CG);
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Reserved.set(MSP430::PCW);
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Reserved.set(MSP430::SPW);
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Reserved.set(MSP430::SRW);
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Reserved.set(MSP430::CGW);
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// Mark frame pointer as reserved if needed.
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if (hasFP(MF))
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Reserved.set(MSP430::FP);
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Reserved.set(MSP430::FPW);
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return Reserved;
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}
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@ -16,37 +16,90 @@ class MSP430Reg<bits<4> num, string n> : Register<n> {
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let Namespace = "MSP430";
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}
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class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs>
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: RegisterWithSubRegs<n, subregs> {
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field bits<4> Num = num;
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let Namespace = "MSP430";
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}
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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def PC : MSP430Reg<0, "r0">;
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def SP : MSP430Reg<1, "r1">;
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def SR : MSP430Reg<2, "r2">;
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def CG : MSP430Reg<3, "r3">;
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def FP : MSP430Reg<4, "r4">;
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def R5 : MSP430Reg<5, "r5">;
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def R6 : MSP430Reg<6, "r6">;
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def R7 : MSP430Reg<7, "r7">;
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def R8 : MSP430Reg<8, "r8">;
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def R9 : MSP430Reg<9, "r9">;
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def R10 : MSP430Reg<10, "r10">;
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def R11 : MSP430Reg<11, "r11">;
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def R12 : MSP430Reg<12, "r12">;
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def R13 : MSP430Reg<13, "r13">;
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def R14 : MSP430Reg<14, "r14">;
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def R15 : MSP430Reg<15, "r15">;
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def PCB : MSP430Reg<0, "r0">;
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def SPB : MSP430Reg<1, "r1">;
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def SRB : MSP430Reg<2, "r2">;
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def CGB : MSP430Reg<3, "r3">;
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def FPB : MSP430Reg<4, "r4">;
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def R5B : MSP430Reg<5, "r5">;
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def R6B : MSP430Reg<6, "r6">;
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def R7B : MSP430Reg<7, "r7">;
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def R8B : MSP430Reg<8, "r8">;
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def R9B : MSP430Reg<9, "r9">;
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def R10B : MSP430Reg<10, "r10">;
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def R11B : MSP430Reg<11, "r11">;
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def R12B : MSP430Reg<12, "r12">;
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def R13B : MSP430Reg<13, "r13">;
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def R14B : MSP430Reg<14, "r14">;
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def R15B : MSP430Reg<15, "r15">;
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// FIXME: we need subregs & special handling for 8 bit stuff
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def PCW : MSP430RegWithSubregs<0, "r0", [PCB]>;
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def SPW : MSP430RegWithSubregs<1, "r1", [SPB]>;
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def SRW : MSP430RegWithSubregs<2, "r2", [SRB]>;
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def CGW : MSP430RegWithSubregs<3, "r3", [CGB]>;
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def FPW : MSP430RegWithSubregs<4, "r4", [FPB]>;
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def R5W : MSP430RegWithSubregs<5, "r5", [R5B]>;
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def R6W : MSP430RegWithSubregs<6, "r6", [R6B]>;
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def R7W : MSP430RegWithSubregs<7, "r7", [R7B]>;
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def R8W : MSP430RegWithSubregs<8, "r8", [R8B]>;
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def R9W : MSP430RegWithSubregs<9, "r9", [R9B]>;
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def R10W : MSP430RegWithSubregs<10, "r10", [R10B]>;
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def R11W : MSP430RegWithSubregs<11, "r11", [R11B]>;
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def R12W : MSP430RegWithSubregs<12, "r12", [R12B]>;
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def R13W : MSP430RegWithSubregs<13, "r13", [R13B]>;
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def R14W : MSP430RegWithSubregs<14, "r14", [R14B]>;
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def R15W : MSP430RegWithSubregs<15, "r15", [R15B]>;
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def : SubRegSet<1, [PCW, SPW, SRW, CGW, FPW,
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R5W, R6W, R7W, R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
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[PCB, SPB, SRB, CGB, FPB,
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R5B, R6B, R7B, R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
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def GR8 : RegisterClass<"MSP430", [i8], 8,
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// Volatile registers
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[R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B,
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// Frame pointer, sometimes allocable
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FPB,
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// Volatile, but not allocable
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PCB, SPB, SRB, CGB]>
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{
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let MethodProtos = [{
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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GR8Class::iterator
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GR8Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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// Depending on whether the function uses frame pointer or not, last 5 or 4
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// registers on the list above are reserved
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if (RI->hasFP(MF))
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return end()-5;
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else
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return end()-4;
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}
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}];
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}
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def GR16 : RegisterClass<"MSP430", [i16], 16,
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// Volatile registers
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[R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
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[R12W, R13W, R14W, R15W, R11W, R10W, R9W, R8W, R7W, R6W, R5W,
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// Frame pointer, sometimes allocable
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FP,
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FPW,
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// Volatile, but not allocable
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PC, SP, SR, CG]>
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PCW, SPW, SRW, CGW]>
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{
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let SubRegClassList = [GR8];
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let MethodProtos = [{
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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