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Run LiveDebugVariables in RegAllocBasic and RegAllocGreedy.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128935 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-04-05 21:40:37 +00:00
parent 0f310ee3c2
commit cfafc54040
11 changed files with 24 additions and 1 deletions
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7
lib/CodeGen/RegAllocBasic.cpp
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@ -13,6 +13,7 @@
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "regalloc"
#include "LiveDebugVariables.h"
#include "LiveIntervalUnion.h"
#include "LiveRangeEdit.h"
#include "RegAllocBase.h"
@ -137,6 +138,7 @@ char RABasic::ID = 0;
} // end anonymous namespace
RABasic::RABasic(): MachineFunctionPass(ID) {
initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
@ -155,6 +157,8 @@ void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<AliasAnalysis>();
AU.addRequired<LiveIntervals>();
AU.addPreserved<SlotIndexes>();
AU.addRequired<LiveDebugVariables>();
AU.addPreserved<LiveDebugVariables>();
if (StrongPHIElim)
AU.addRequiredID(StrongPHIEliminationID);
AU.addRequiredTransitive<RegisterCoalescer>();
@ -543,6 +547,9 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
// Run rewriter
VRM->rewrite(LIS->getSlotIndexes());
// Write out new DBG_VALUE instructions.
getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
// The pass output is in VirtRegMap. Release all the transient data.
releaseMemory();

7
lib/CodeGen/RegAllocGreedy.cpp
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@ -15,6 +15,7 @@
#define DEBUG_TYPE "regalloc"
#include "AllocationOrder.h"
#include "InterferenceCache.h"
#include "LiveDebugVariables.h"
#include "LiveRangeEdit.h"
#include "RegAllocBase.h"
#include "Spiller.h"
@ -196,6 +197,7 @@ FunctionPass* llvm::createGreedyRegisterAllocator() {
}
RAGreedy::RAGreedy(): MachineFunctionPass(ID), LRStage(RS_New) {
initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
@ -218,6 +220,8 @@ void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<LiveIntervals>();
AU.addRequired<SlotIndexes>();
AU.addPreserved<SlotIndexes>();
AU.addRequired<LiveDebugVariables>();
AU.addPreserved<LiveDebugVariables>();
if (StrongPHIElim)
AU.addRequiredID(StrongPHIEliminationID);
AU.addRequiredTransitive<RegisterCoalescer>();
@ -1183,6 +1187,9 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
VRM->rewrite(Indexes);
}
// Write out new DBG_VALUE instructions.
getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
// The pass output is in VirtRegMap. Release all the transient data.
releaseMemory();

1
test/CodeGen/X86/2010-05-25-DotDebugLoc.ll
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@ -1,4 +1,5 @@
; RUN: llc -march=x86-64 -O2 < %s | FileCheck %s
; RUN: llc -march=x86-64 -O2 -regalloc=basic < %s | FileCheck %s
; Test to check .debug_loc support. This test case emits many debug_loc entries.
; CHECK: Loc expr size

1
test/CodeGen/X86/2010-05-26-DotDebugLoc.ll
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@ -1,4 +1,5 @@
; RUN: llc -O2 < %s | FileCheck %s
; RUN: llc -O2 -regalloc=basic < %s | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin"

1
test/CodeGen/X86/2010-05-28-Crash.ll
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@ -1,4 +1,5 @@
; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s
; RUN: llc -mtriple=x86_64-apple-darwin -regalloc=basic < %s | FileCheck %s
; Test to check separate label for inlined function argument.
define i32 @foo(i32 %y) nounwind optsize ssp {

1
test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll
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@ -1,4 +1,5 @@
; RUN: llc -O2 < %s | FileCheck %s
; RUN: llc -O2 -regalloc=basic < %s | FileCheck %s
; Test to check that unused argument 'this' is not undefined in debug info.
target triple = "x86_64-apple-darwin10.2"

1
test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll
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@ -1,4 +1,5 @@
; RUN: llc < %s | FileCheck %s
; RUN: llc < %s -regalloc=basic | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin10.0.0"

1
test/CodeGen/X86/dbg-merge-loc-entry.ll
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@ -1,4 +1,5 @@
; RUN: llc < %s | FileCheck %s
; RUN: llc < %s -regalloc=basic | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin8"

1
test/CodeGen/X86/dbg-value-inlined-parameter.ll
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@ -1,4 +1,5 @@
; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s
; RUN: llc -mtriple=x86_64-apple-darwin -regalloc=basic < %s | FileCheck %s
;CHECK: DW_TAG_inlined_subroutine
;CHECK-NEXT: DW_AT_abstract_origin

1
test/CodeGen/X86/dbg-value-location.ll
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@ -1,4 +1,5 @@
; RUN: llc < %s | FileCheck %s
; RUN: llc < %s -regalloc=basic | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin10.0.0"
;Radar 8950491

1
test/CodeGen/X86/dbg-value-range.ll
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@ -1,4 +1,5 @@
; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s
; RUN: llc -mtriple=x86_64-apple-darwin -regalloc=basic < %s | FileCheck %s
%struct.a = type { i32 }